US3816765A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital interface circuit for a random noise generator
Assignee: RCA Corp
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Filing: 1973-04-30
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Granted: 1974-06-11
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Expires: 1993-04-30
Abstract
Abstract An interface circuit arrangement between a random noise generator circuit and an output digital logic integrated circuit. The interface circuit includes a digital logic integrated circuit which has impedance levels and voltage levels compatible with that of the output digital logic integrated circuit and which is connected within a closed loop including a differential amplifier which biases the interface digital logic integrated circuit into a symmetrical amplification region substantially midway within its linear range of operation thereby removing a threshold selectivity which otherwise reduces the randomness of the output of the random noise generator.
Inventors
- 👤 R Goyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0175; H03K19/017545; H03K3/00; H03K3/84
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
252 words
An interface circuit for coupling an input AC signal to an output logic circuit, comprising: a logic circuit compatible with said output logic circuit, said logic circuit having an input terminal and an output terminal, said output terminal being coupled to an input terminal of said output logic circuit, said logic circuit including an amplifier directly coupled to said input terminal; a differential amplifier having first and second input terminals and an output terminal, said fIrst input terminal adapted to receive said input AC signal, said output terminal being coupled to said input terminal of said logic circuit; a DC path coupling said output terminal of said logic circuit to said first and second input terminals for applying substantially equal portions of an output interface signal generated at said output terminal of said logic circuit to said first and second input terminals, said differential amplifier generating a signal in response to said output interface signal to cause said logic circuit to operate substantially midway in its linear region of operation whenever said output interface signal exceeds a first predetermined value while changing in a first sense; AC impedance means for attenuating AC signals coupled to said second terminal; and means for biasing said differential amplifier to prevent signals at said input terminal of said logic circuit from exceeding a second predetermined value to cause said logic circuit to operate substantially midway in its linear region of operation while said output interface signals is changing in a sense opposite to said first sense.
Claim 2
Dependent Claim
252 words
An interface circuit for coupling an input AC signal to an output logic circuit, comprising: a logic circuit compatible with said output logic circuit, said logic circuit having an input terminal and an output terminal, said output terminal being coupled to an input terminal of said output logic circuit, said logic circuit including an amplifier directly coupled to said input terminal; a differential amplifier having first and second input terminals and an output terminal, said fIrst input terminal adapted to receive said input AC signal, said output terminal being coupled to said input terminal of said logic circuit; a DC path coupling said output terminal of said logic circuit to said first and second input terminals for applying substantially equal portions of an output interface signal generated at said output terminal of said logic circuit to said first and second input terminals, said differential amplifier generating a signal in response to said output interface signal to cause said logic circuit to operate substantially midway in its linear region of operation whenever said output interface signal exceeds a first predetermined value while changing in a first sense; AC impedance means for attenuating AC signals coupled to said second terminal; and means for biasing said differential amplifier to prevent signals at said input terminal of said logic circuit from exceeding a second predetermined value to cause said logic circuit to operate substantially midway in its linear region of operation while said output interface signals is changing in a sense opposite to said first sense.
Claim 3
Dependent Claim
93 words
The interface circuit recited in claim 1 wherein said differential amplifier comprises: first and second transistor of the same conductivity type having base, emitter, and collector electrodes, said base electrode of said first transistor being coupled to said first input terminal, said base electrode of said second transistor being coupled to said second input signal, said emitter electrodes being coupled to said biasing means, said collector of said first transistor being adapted to receive a first fixed potential, said collector of said second transistor being coupled to said input of said logic circuit.
Claim 4
Dependent Claim
42 words
The interface circuit recited in claim 2 wherein said biasing means includes means for applying a second fixed potential and a bias resistor coupled between said emitters of said first and second transistor and said means for applying said second fixed potential.
Claim 5
Dependent Claim
55 words
The interface circuit recited in claim 3 wherein the semiconductor junction between said base and said collector of said second transistor conducts whenever said output interface signal exceeds said first predetermined value and said bias resistor is selected to prevent signals at said input terminal of said logic circuit from exceeding said second predetermined value.
Claim 6
Dependent Claim
53 words
The interface circuit recited in claim 4 wherein said DC path comprises: first and second resistor of substantial equal value connected in series between said first and second input terminals; and a third resistor connected between the common junction point of said first and second resistors and said output of said logic circuit.
Claim 7
Dependent Claim
68 words
The interface circuit recited in claim 5 wherein said AC impedance means comprises: a first capacitor connected between said common junction point of said first and second resistor, said third resistor and said first capacitor forming a low pass filter to prevent said interface circuit from oscillating; and a second capacitor connected between said second input terminal and said common junction point of said first and second resistors.
Claim 8
Dependent Claim
22 words
The interface circuit recited in claim 6 wherein said logic circuit and said output logic circuit are of the same logic family.
Claim 9
Dependent Claim
25 words
The interface circuit recited in claim 7 wherein said logic circuit and said output logic circuit are each a NAND gate having an extender input.
Claim 10
Dependent Claim
105 words
The interface circuit recited in claim 8 wherein said input signal is a random noise signal generated by a circuit having an output terminal coupled to said first input terminal and comprising: a random noise source for generating a random noise signal consisting essentially of pulses occurring at random intervals, having random durations and amplitudes; amplifier means adapted to equally amplify positive and negative going signals; a high pass filter circuit coupling said random noise signal to The input of said amplifier; and means for coupling only the AC portions of the signal generated at the output of said amplifier to said first input terminal.
Claim 11
Dependent Claim
36 words
The circuit recited in claim 9 wherein said random noise source includes a zener noise source and means to bias said zener noise source in its avalanche region of operation to generate said random noise signals.
Claim 12
Dependent Claim
132 words
A random noise circuit comprising: a random noise source for generating a random noise signal consisting essentially of pulses having random durations and amplitudes and occurring at random intervals; amplifier means responsive to said random noise signal for equally amplifying positive going and negative going portions of said random noise signal and generating an amplified random noise signal; an output logic circuit; and interface means including a logic circuit compatible with said output logic circuit responsive to said amplified random noise signal for equally amplifying positive going and negative going portions of said amplified random noise signal and interfacing said amplifier means to said output logic circuit; said output logic circuit generating a random noise signal consisting essentially of pulses having random durations and substantially uniform amplitudes and occurring at random intervals.
Claim 13
Dependent Claim
132 words
A random noise circuit comprising: a random noise source for generating a random noise signal consisting essentially of pulses having random durations and amplitudes and occurring at random intervals; amplifier means responsive to said random noise signal for equally amplifying positive going and negative going portions of said random noise signal and generating an amplified random noise signal; an output logic circuit; and interface means including a logic circuit compatible with said output logic circuit responsive to said amplified random noise signal for equally amplifying positive going and negative going portions of said amplified random noise signal and interfacing said amplifier means to said output logic circuit; said output logic circuit generating a random noise signal consisting essentially of pulses having random durations and substantially uniform amplitudes and occurring at random intervals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-10 | 1977-12-10 | 1978-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-10 | 1981-12-10 | 1982-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-10 | 1985-12-10 | 1986-06-11 | $7700.00 | Window Closed / Lapsed |