Patent US4042834A successfully refreshed from Google Patents.
US4042834A
Expired / Lapsed
US
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Frequency doubler circuit
Assignee: Motorola Solutions Inc
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Filing: 1976-07-22
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Granted: 1977-08-16
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Expires: 1996-07-22
Abstract
Abstract The frequency doubler includes circuits for charging and discharging a capacitor at a predetermined rate in response to each incoming cycle. First and second comparators are connected between the capacitor and the input of an OR gate. These comparators limit the magnitudes of the charged voltage and the discharged voltage of the capacitor. The OR gate responds to both comparators being off during a part of the rising portion of the capacitor waveform and during a part of the falling portion of the capacitor waveform by providing pulses having twice the repetition rate as the input pulses. An output circuit may be connected to the output terminal of the OR gate for converting the output signal of the OR gate into a further output signal comprised of current pulses having constant amplitude and duration.
Inventors
- 👤 W. David Pace
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:39
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/56; G01P3/60; B; B60; B60T; B60T8/00; B60T8/17; B60T8/172; G01P3/44; G01P3/48; G01P3/4802; G01P3/4805; H; H03; H03K; H03K5/00; H03K5/00006
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
133 words
A frequency doubler circuit comprising: means for providing a capacitance; means for charging and discharging said capacitance in response to input pulses; means for providing a first reference potential of a first predetermined magnitude and a second reference potential of a second predetermined magnitude; Oring means; first transistor means having main electrodes and a control electrode, said main electrodes being directly coupled between said means for providing a capacitance and said ORing means, said control electrode being adapted to receive said first reference potential; and second transistor means having main electrodes and a control electrode, said main electrodes of said second transistor means being directly coupled between said means for providing a capacitance and said ORing means, said control electrode of said second transistor means being adapted to receive said second reference potential.
Claim 2
Dependent Claim
133 words
A frequency doubler circuit comprising: means for providing a capacitance; means for charging and discharging said capacitance in response to input pulses; means for providing a first reference potential of a first predetermined magnitude and a second reference potential of a second predetermined magnitude; Oring means; first transistor means having main electrodes and a control electrode, said main electrodes being directly coupled between said means for providing a capacitance and said ORing means, said control electrode being adapted to receive said first reference potential; and second transistor means having main electrodes and a control electrode, said main electrodes of said second transistor means being directly coupled between said means for providing a capacitance and said ORing means, said control electrode of said second transistor means being adapted to receive said second reference potential.
Claim 3
Dependent Claim
169 words
The frequency doubler circuit of claim 1 wherein said means for charging and discharging said capacitance includes: current supply means for providing a current of a first predetermined magnitude, said current supply means being coupled to said means for providing a capacitance; current drain means for drawing a current having a second predetermined magnitude which is less than said first predetermined magnitude from said capacitance, said current drain means being connected to said means for providing a capacitance; and third transistor means having main electrodes connected with said current supply means and a control electrode adapted for receiving control signals, said third transistor means being rendered conductive in response to said control signals of a first level to shunt current from said current supply means away from said capacitance so that said capacitance discharges and said third transistor means being rendered nonconductive in response to said control signals of a second level to allow the current from said current supply means to charge said capacitance at a predetermined rate.
Claim 4
Dependent Claim
33 words
The frequency doubler circuit of claim 1 wherein said first transistor means includes emitter and collector electrodes corresponding to said main electrodes thereof and a base electrode corresponding to said control electrode thereof.
Claim 5
Dependent Claim
84 words
The frequency doubler circuit of claim 1 wherein said second transistor means includes first and second collector electrodes corresponding to said main electrodes thereof and an emitter electrode corresponding to said control electrode thereof, and a base electrode, said base electrode of said second transistor means being connected to said first collector electrode thereof and said second collector electrode of said second transistor means being coupled to said ORing means, said first collector electrode further being coupled to said means for providing a capacitance.
Claim 6
Dependent Claim
20 words
The frequency doubler circuit of claim 16 further including current converter circuit coupled to the output of said ORing means.
Claim 7
Dependent Claim
87 words
The frequency doubler circuit of claim 5 wherein said current converter circuit includes: additional electron control means having a control electrode and main electrodes, said control electrode of said additional electron control means being coupled to said ORing means; current supply means coupled in series with said main electrodes of said additional electron control means; and further electron control means having a control electrode connected to said output terminal of said current supply means and main electrodes for providing an output signal for the frequency doubler circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |