Patent US4041333A successfully refreshed from Google Patents.
US4041333A
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High speed input buffer circuit
Assignee: Intel Corp
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Filing: 1975-12-15
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Granted: 1977-08-09
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Expires: 1995-12-15
Abstract
Abstract A high speed buffer circuit having an input and complementary outputs includes a pair of feedback transistors for shortening the response time of the output signals at the complementary outputs and a capacitive load at each output for delaying the effect of the output signals on the feedback transistors.
Inventors
- 👤 Eli Porat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:33
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; H03K3/356069
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
142 words
A high speed buffer circuit having an input and true and inverted outputs for receiving an input signal and producing true and inverted output signals therefrom comprising: an input transistor for receiving said input signal: means coupling said input transistor to said outputs, said outputs having capacitive loads coupled thereto; and feedback means coupling said outputs to said input transistor, said feedback means being operable for shortening the response time of said true and inverted output signals at said outputs in response to said input signal at said input, and said capacitive loads being operable for delaying the effect of said output signals on said feedback means, the capacitive loads coupled to said outputs being charged in accordance with the state of said input signal being applied to said input transistor to produce said output signals at said true and inverted outputs.
Claim 2
Dependent Claim
142 words
A high speed buffer circuit having an input and true and inverted outputs for receiving an input signal and producing true and inverted output signals therefrom comprising: an input transistor for receiving said input signal: means coupling said input transistor to said outputs, said outputs having capacitive loads coupled thereto; and feedback means coupling said outputs to said input transistor, said feedback means being operable for shortening the response time of said true and inverted output signals at said outputs in response to said input signal at said input, and said capacitive loads being operable for delaying the effect of said output signals on said feedback means, the capacitive loads coupled to said outputs being charged in accordance with the state of said input signal being applied to said input transistor to produce said output signals at said true and inverted outputs.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said feedback means includes a pair of feedback transistors.
Claim 4
Dependent Claim
18 words
The circuit of claim 2 wherein one of said feedback transistors is directly coupled to said input transistor.
Claim 5
Dependent Claim
59 words
The circuit of claim 1 wherein said means coupling said input transistor to said outputs includes one or more transistors coupled to each of said outputs to pull-up the voltage of said output signals at said outputs and one or more transistors coupled to each of said outputs to pull-down the voltage of said output signals at said outputs.
Claim 6
Dependent Claim
38 words
The circuit of claim 4 wherein said feedback means includes a pair of feedback transistors and wherein said feedback transistors and said pull-up transistors are depletion-type transistors and said input transistor and said pull-down transistors are enhancement-type transistors.
Claim 7
Dependent Claim
12 words
The circuit of claim 5 wherein said transistors are N-type MOS transistors.
Claim 8
Dependent Claim
111 words
In a high speed buffer circuit having an input and at least a first output for receiving an input signal and producing at least a first output signal therefrom, the improvement comprising; feedback means coupling said input and said output for shortening the response time of an output signal at said output in response to an input signal at said input; and capacitive means coupled to said output for delaying the effect of said output signal on said feedback means, said capacitive means coupled to said output being charged in accordance with the state of said input signal being applied to said input to produce an output signal at said output.
Claim 9
Dependent Claim
111 words
In a high speed buffer circuit having an input and at least a first output for receiving an input signal and producing at least a first output signal therefrom, the improvement comprising; feedback means coupling said input and said output for shortening the response time of an output signal at said output in response to an input signal at said input; and capacitive means coupled to said output for delaying the effect of said output signal on said feedback means, said capacitive means coupled to said output being charged in accordance with the state of said input signal being applied to said input to produce an output signal at said output.
Claim 10
Dependent Claim
68 words
The improvement of claim 7 wherein said circuit further includes at least a second complementary output, said second output having a capacitive means coupled thereto, said feedback means coupling said second output to said input, said capacitive means coupled to said second output being charged in accordance with the state of said input signal being applied to said input to produce an output signal at said second output.
Claim 11
Dependent Claim
117 words
A MOS high speed buffer circuit having an input and a pair of complementary outputs for providing true and inverted output signals comprising: an input transistor coupled to said input; a first feedback transistor coupled to said input transistor and said true output; a first pull-up transistor and first and second pulldown transistors coupling said input to said true output; a second feedback transistor coupled to said first pull-down transistor and said inverted output; a second pull-up transistor and third pull-down transistor coupling said input to said inverted output; and Capacitive means coupled to said true and inverted outputs for delaying the effect of said true and inverted output signals on said first and second feedback transistors.
Claim 12
Dependent Claim
117 words
A MOS high speed buffer circuit having an input and a pair of complementary outputs for providing true and inverted output signals comprising: an input transistor coupled to said input; a first feedback transistor coupled to said input transistor and said true output; a first pull-up transistor and first and second pulldown transistors coupling said input to said true output; a second feedback transistor coupled to said first pull-down transistor and said inverted output; a second pull-up transistor and third pull-down transistor coupling said input to said inverted output; and Capacitive means coupled to said true and inverted outputs for delaying the effect of said true and inverted output signals on said first and second feedback transistors.
Claim 13
Dependent Claim
37 words
The circuit of claim 9 wherein said first and second feedback transistors and said first and second pull-up transistors are depletion-type transistors and said input transistor and said first, second and third pull-down transistors are enhancement-type transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-08 | 1981-02-07 | 1981-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-08 | 1985-02-07 | 1985-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-08 | 1989-02-07 | 1989-08-09 | $7700.00 | Window Closed / Lapsed |