Patent US4038564A successfully refreshed from Google Patents.
US4038564A
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Multi-level voltage selection circuit
Assignee: Casio Computer Co Ltd
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Filing: 1976-02-17
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Granted: 1977-07-26
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Expires: 1996-02-17
Abstract
Abstract A voltage selection circuit comprises CMOS circuits, each comprised of a series of P-channel MOS transistors and a series of N-channel MOS transistors. In each CMOS circuit, the gate electrodes of the P-channel MOS transistors are connected to those of the N-channel MOS transistors, respectively, to thereby form pairs of P- and N-channel transistors. Binary coded signals are supplied to the gate electrodes of the MOS transistors. In each CMOS circuit, upon receipt of binary coded signals at the pairs of P- and N-channel MOS transistors, only P-channel transistors or only N-channel transistors are turned on one after another. The voltage between the open source electrodes of each CMOS circuit can pass through the P-channel transistors or the N-channel transistors, thereby enabling selection of one of at least four different voltages based on the input binary coded signals.
Inventors
- 👤 Masayuki Hakata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:57
CPC Classifications
G; G01; G01R; G01R13/00; G09; G09G; G09G3/00; G09G3/04; G09G3/16; G09G3/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
322 words
A multi-level voltage selection circuit comprising: two CMOS circuits, each including a pair of P-channel MOS transistors serially connected in source-to-drain fashion, and a pair of N-channel MOS transistors serially connected in source-to-drain fashion and having their gate electrodes connected to those of said P-channel MOS transistors, respectively, thereby forming two pairs of P- and N-channel MOS transistors, and the open drain electrode of said pair of N-channel MOS transistors being connected to that of said pair of P-channel MOS transistors; an output terminal connected to the junctions between the P-channel MOS transistors and N-channel MOS transistors of said two CMOS circuits; two gate control terminals, one of said gate control terminals being connected to the gate electrodes of one pair of P- and N-channel MOS transistors of one of said CMOS circuits and to those of one pair of P- and N-channel MOS transistors of the other CMOS circuit, and the other of said gate control terminals being connected to the gate electrodes of the other pair of P- and N-channel MOS transistors of one of said CMOS circuits and to those of the other pair of P- and N-channel MOS transistors of the other CMOS circuit, said gate control terminals receiving 1-bit binary coded signals; a logic circuit including one inverter and connected between said gate control terminals and the gate electrodes of said P- and N-channel MOS transistors so as to supply said 1-bit binary coded signals to the gate electrodes of both pairs of P- and N-channel MOS transistors of one of said CMOS circuits and the gate electrodes of one pair of P- and N-channel MOS transistors of the other CMOS circuit and said 1-bit binary coded signals inverted by said inverter to the gate electrodes of the other pair of P- and N-channel transistors of the other CMOS circuit; and four selection voltage supplying terminals connected to the open source electrodes of said CMOS circuits, respectively.
Claim 2
Dependent Claim
322 words
A multi-level voltage selection circuit comprising: two CMOS circuits, each including a pair of P-channel MOS transistors serially connected in source-to-drain fashion, and a pair of N-channel MOS transistors serially connected in source-to-drain fashion and having their gate electrodes connected to those of said P-channel MOS transistors, respectively, thereby forming two pairs of P- and N-channel MOS transistors, and the open drain electrode of said pair of N-channel MOS transistors being connected to that of said pair of P-channel MOS transistors; an output terminal connected to the junctions between the P-channel MOS transistors and N-channel MOS transistors of said two CMOS circuits; two gate control terminals, one of said gate control terminals being connected to the gate electrodes of one pair of P- and N-channel MOS transistors of one of said CMOS circuits and to those of one pair of P- and N-channel MOS transistors of the other CMOS circuit, and the other of said gate control terminals being connected to the gate electrodes of the other pair of P- and N-channel MOS transistors of one of said CMOS circuits and to those of the other pair of P- and N-channel MOS transistors of the other CMOS circuit, said gate control terminals receiving 1-bit binary coded signals; a logic circuit including one inverter and connected between said gate control terminals and the gate electrodes of said P- and N-channel MOS transistors so as to supply said 1-bit binary coded signals to the gate electrodes of both pairs of P- and N-channel MOS transistors of one of said CMOS circuits and the gate electrodes of one pair of P- and N-channel MOS transistors of the other CMOS circuit and said 1-bit binary coded signals inverted by said inverter to the gate electrodes of the other pair of P- and N-channel transistors of the other CMOS circuit; and four selection voltage supplying terminals connected to the open source electrodes of said CMOS circuits, respectively.
Claim 3
Dependent Claim
260 words
A multi-level voltage selection circuit comprising: at least two CMOS circuits, each including (i) a group of P-channel MOS transistors serially connected in source-to-drain fashion, each group thus having an open drain electrode and an open source electrode, and (ii) a group of N-channel MOS transistors in the same number as said P-channel MOS transistors, serially connected in source-to-drain fashion so as to have an open drain electrode and an open source electrode, the open drain electrode of said N-channel MOS transistor group being connected to that of said P-channel MOS transistor group, the gate electrode of each P-channel MOS transistor being connected to that of a corresponding N-channel MOS transistor, thus forming a pair of P- and N-channel MOS transistors; an output terminal connected to the junctions between the P- and N-channel MOS transistor groups in said CMOS circuits; at least two gate control terminals, each gate control terminal supplying binary coded signals to the gate electrodes of the MOS transistors of each CMOS circuit; a logic circuit connected between said gate control terminals and the gate electrodes of the MOS transistors of said CMOS circuits so as to supply the binary coded signals supplied to said gate control terminals to the gate electrodes of the MOS transistors of one of said CMOS circuits and binary coded signals complementary to those supplied to said gate control terminals to the gate electrodes of the MOS transistors of the other CMOS circuit; and at least four selection voltage supplying terminals connected to the open source electrodes of said CMOS circuits, respectively.
Claim 4
Dependent Claim
260 words
A multi-level voltage selection circuit comprising: at least two CMOS circuits, each including (i) a group of P-channel MOS transistors serially connected in source-to-drain fashion, each group thus having an open drain electrode and an open source electrode, and (ii) a group of N-channel MOS transistors in the same number as said P-channel MOS transistors, serially connected in source-to-drain fashion so as to have an open drain electrode and an open source electrode, the open drain electrode of said N-channel MOS transistor group being connected to that of said P-channel MOS transistor group, the gate electrode of each P-channel MOS transistor being connected to that of a corresponding N-channel MOS transistor, thus forming a pair of P- and N-channel MOS transistors; an output terminal connected to the junctions between the P- and N-channel MOS transistor groups in said CMOS circuits; at least two gate control terminals, each gate control terminal supplying binary coded signals to the gate electrodes of the MOS transistors of each CMOS circuit; a logic circuit connected between said gate control terminals and the gate electrodes of the MOS transistors of said CMOS circuits so as to supply the binary coded signals supplied to said gate control terminals to the gate electrodes of the MOS transistors of one of said CMOS circuits and binary coded signals complementary to those supplied to said gate control terminals to the gate electrodes of the MOS transistors of the other CMOS circuit; and at least four selection voltage supplying terminals connected to the open source electrodes of said CMOS circuits, respectively.
Claim 5
Dependent Claim
38 words
A multi-level voltage selection circuit according to claim 2, wherein said logic circuit comprises a number of inverters the number of which is expressed as "X - 1", where "X" denotes the number of said gate control terminals.
Claim 6
Dependent Claim
36 words
A multi-level voltage selection circuit according to claim 2, wherein the number of MOS transistors comprising each CMOS circuit is expressed as "X 2 . X", where "X" denotes the number of said gate control terminals.
Claim 7
Dependent Claim
115 words
A multi-level voltage selection circuit according to claim 2, wherein the number of said selection voltage supplying terminals is expressed as "2 x "; said logic circuit comprises a number of inverters the number of which is expressed as "X - 1"; and the number of MOS transistors comprising each CMOS circuit is expressed as "2 x . X", where "X" denotes the number of said gate control terminals; said logic circuit supplying the binary coded signals supplied to the gate control terminals to the MOS transistors of one of said CMOS circuits and binary coded signals complementary to those supplied to said gated control terminals to the MOS transistors of the other CMOS circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-25 | 1981-01-24 | 1981-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-25 | 1985-01-24 | 1985-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-25 | 1989-01-24 | 1989-07-26 | $7700.00 | Window Closed / Lapsed |