Patent US4037308A successfully refreshed from Google Patents.
US4037308A
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US
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Methods for making transistor structures
Assignee: AT&T Inc
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Filing: 1976-11-03
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Granted: 1977-07-26
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Expires: 1996-11-03
Abstract
Abstract In one embodiment, an extremely short channel FET is made by forming a metal layer over a wafer, depositing silicon dioxide over part of the metal layer, oxidizing the exposed metal, controllably etching a portion of the silicon dioxide to expose a small strip of the nonoxidized metal layer, electroplating the exposed metal strip, thereby to form an extremely narrow gate electrode, removing the deposited SiO 2 , the metal oxide and the remaining metal layer to leave only the gate electrode, and using the gate electrode as a mask for ion implanting source and drain regions. Since the gate electrode can be made so narrow, the channel region is correspondingly short to give extremely high frequency capabilities. Other embodiments are also described.
Inventors
- 👤 George Elwood Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:34
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D99/00; H10P; H10P14/00; H10P14/60; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/117; Y10S148/143; Y10S438/00; Y10S438/942; Y10S438/945; Y10S438/947
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
119 words
A method for making transistors comprising: the steps of forming over a semiconductor substrate a first mask having an exposed portion which includes a first vertical edge; forming a first impurity region in the substrate at a location defined by the first vertical edge of the first mask; forming a second mask which has a first vertical edge which abuts the first vertical edge of the first mask; controllably increasing the lateral extent of the second mask to cause the first vertical edge thereof to be extended by a controllable amount to define a second vertical edge; and forming a second impurity region in the substrate at a location defined by the second vertical edge of the second mask.
Claim 2
Independent Claim
119 words
A method for making transistors comprising: the steps of forming over a semiconductor substrate a first mask having an exposed portion which includes a first vertical edge; forming a first impurity region in the substrate at a location defined by the first vertical edge of the first mask; forming a second mask which has a first vertical edge which abuts the first vertical edge of the first mask; controllably increasing the lateral extent of the second mask to cause the first vertical edge thereof to be extended by a controllable amount to define a second vertical edge; and forming a second impurity region in the substrate at a location defined by the second vertical edge of the second mask.
Claim 3
Dependent Claim
61 words
The method of claim 1 wherein: the first mask is silicon dioxide (e.g., 63) which is used as a ion implantation mask to define the location of the first impurity region (e.g., 66); and the second edge (68) is part of a metal layer used as an ion implantation mask to define the location of the second impurity region (e.g., 69).
Claim 4
Independent Claim
180 words
A method for making a transistor comprising the steps of: forming over a semiconductor substrate a thin oxide layer (e.g., 61); forming over the oxide layer a first thin metal layer (e.g., 62); forming on part of the thin metal layer a first mask having a first edge (e.g., 64); ion implanting a first impurity region (e.g., 66) in the substrate using the first mask as an ion implant mask; depositing a second metal layer (e.g., 65) on the first metal layer such that it abuts against the first edge; removing the first mask and that portion of the first metal layer not covered by the second metal layer; electrochemically plating a third metal layer (e.g., 67) over the exposed surface of the first and second metal layers, whereby the third metal layer has a second edge (e.g., 68) laterally removed from the location of the first edge by a distance substantially equal to the thickness of the third metal layer; and ion implanting a second impurity region (e.g., 69) using the third metal layer as an ion implant mask.
Claim 5
Independent Claim
180 words
A method for making a transistor comprising the steps of: forming over a semiconductor substrate a thin oxide layer (e.g., 61); forming over the oxide layer a first thin metal layer (e.g., 62); forming on part of the thin metal layer a first mask having a first edge (e.g., 64); ion implanting a first impurity region (e.g., 66) in the substrate using the first mask as an ion implant mask; depositing a second metal layer (e.g., 65) on the first metal layer such that it abuts against the first edge; removing the first mask and that portion of the first metal layer not covered by the second metal layer; electrochemically plating a third metal layer (e.g., 67) over the exposed surface of the first and second metal layers, whereby the third metal layer has a second edge (e.g., 68) laterally removed from the location of the first edge by a distance substantially equal to the thickness of the third metal layer; and ion implanting a second impurity region (e.g., 69) using the third metal layer as an ion implant mask.
References Cited (Backward Citations)
US3514844A
Cited
US3699646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-25 | 1981-01-24 | 1981-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-25 | 1985-01-24 | 1985-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-25 | 1989-01-24 | 1989-07-26 | $7700.00 | Window Closed / Lapsed |