US4037217A
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Read-only memory using complementary conductivity type insulated gate field effect transistors
Assignee: Texas Instruments Inc
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Filing: 1975-09-12
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Granted: 1977-07-19
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Expires: 1995-09-12
Abstract
Abstract A read-only memory, comprising a decoder and a storage memory, wherein the decoder matrix and the storage memory matrix each comprises complementary metal oxide semiconductor transistors. Each column of the decoder matrix and each column of the storage memory matrix is connected to a single load or precharge transistor.
Inventors
- 👤 Giuseppe Savarese
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:09
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
324 words
A read-only semiconductor memory comprising insulated gate field effect transistors and including a decoder matrix and a storage memory matrix, wherein said decoder matrix and said storage memory matrix each comprises complementary conductivity type insulated gate field effect transistors; said decoder matrix including a plurality of intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor said intersection transistors all having the same channel conductivity type, each row of said decoder matrix including a plurality of said first transistors and complementary conductivity type insulated gate field effect transistor gate means connecting the gates of said row transistors to a respectively corresponding address input, means connecting an interrogation input for said decoder matrix directly to the gate of one of the transistors of said transfer gate means and means including a complementary conductivity type insulated gate field effect transistor inverter means for connecting said interrogation inputs to the gate of the other transfer gate transistor; each said row transistor also forming part of a different column of said decoder matrix and including a channel connected in common with the channels of other transistors of said column, said other transistors forming part of the other rows of said decoder matrix; for each column of said decoder matrix a single precharge insulated gate field effect transistor of opposite channel conductivity type from that of said intersection transistors connecting the channels of the transistors of that said column to a d.c. supply line; and means connecting the columns of said decoder matrix to respective rows of said storage memory matrix, said storage memory matrix comprising a plurality of intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor, said storage memory matrix intersection transistors all having the same conductivity type, and for each column of the storage memory matrix a single load transistor of opposite conductivity type from that of said storage memory matrix intersection transistors.
Claim 2
Dependent Claim
324 words
A read-only semiconductor memory comprising insulated gate field effect transistors and including a decoder matrix and a storage memory matrix, wherein said decoder matrix and said storage memory matrix each comprises complementary conductivity type insulated gate field effect transistors; said decoder matrix including a plurality of intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor said intersection transistors all having the same channel conductivity type, each row of said decoder matrix including a plurality of said first transistors and complementary conductivity type insulated gate field effect transistor gate means connecting the gates of said row transistors to a respectively corresponding address input, means connecting an interrogation input for said decoder matrix directly to the gate of one of the transistors of said transfer gate means and means including a complementary conductivity type insulated gate field effect transistor inverter means for connecting said interrogation inputs to the gate of the other transfer gate transistor; each said row transistor also forming part of a different column of said decoder matrix and including a channel connected in common with the channels of other transistors of said column, said other transistors forming part of the other rows of said decoder matrix; for each column of said decoder matrix a single precharge insulated gate field effect transistor of opposite channel conductivity type from that of said intersection transistors connecting the channels of the transistors of that said column to a d.c. supply line; and means connecting the columns of said decoder matrix to respective rows of said storage memory matrix, said storage memory matrix comprising a plurality of intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor, said storage memory matrix intersection transistors all having the same conductivity type, and for each column of the storage memory matrix a single load transistor of opposite conductivity type from that of said storage memory matrix intersection transistors.
Claim 3
Dependent Claim
61 words
A memory according to claim 1, wherein said intersection transistors of said decoder matrix have a channel conductivity type opposite from that of said storage memory matrix intersection transistors, and each said means connecting a column of said decoder matrix with a corresponding row of said storage memory matrix includes a complementary conductivity type insulated gate field effect transistor inverter circuit.
Claim 4
Dependent Claim
119 words
A memory according to claim 1, wherein said storage memory matrix includes a read input, and complementary conductivity type field effect transistor input circuit for connecting said decoder matrix columns to said storage matrix rows, wherein columns of said storage matrix each includes insulated gate field effect transistors having channels connected between a column conductor and a d.c. supply line defining a binary logic level, means connecting gates of selected ones of said column transistors to respective row conductors of said storage memory matrix to define a predetermined read only memory code pattern therein, and the channels of said transistors of a same column of said storage memory matrix being commonly connected to a load transistor for that column.
Claim 5
Dependent Claim
92 words
A memory according to claim 3, wherein said input circuit for each row of said storage memory matrix comprises a complementary conductivity type insulated gate field effect transistor transfer gate, one of the transistors of said transfer gate having a gate connected to said read input of said storage memory matrix, and a complementary conductivity type insulated gate field effect transistor inverter circuit connecting said read input to the gate of the other transfer gate transistor and to the gates of said load transistors of each column of said storage memory matrix.
Claim 6
Dependent Claim
244 words
A read-only semiconductor memory comprising insulated gate field effect transistors and including a decoder matrix and a storage memory matrix, wherein said decoder matrix and said storage memory matrix each comprises intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor; said decoder matrix including a. an interrogation input, b. a plurality of input circuits, c. each row of said decoder matrix including n-channel transistors having gates connected by a said input circuit to a respective corresponding address input, each said row transistor forming part of a different column of said decoder matrix and having a channel connected to the channel of the other transistors of said column, d. the channels of said transistors of a same column being connected by a common p-channel precharge transistor to a d.c. supply line, e. each said input circuit comprising a transfer gate including an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor, said n-channel transistor having a gate connected to an interrogation input, and a complementary conductivity type insulated gate field effect transistor inverter circuit connecting said interrogation input to a gate of said p-channel transistor of said transfer gate, and f. a decoder matrix output connected to each individual column thereof; said storage memory matrix including: 1. a read input, 2. a plurality of input circuit means for connecting respective column outputs of said decoder matrix to respective rows of said storage matrix,
Claim 7
Dependent Claim
244 words
A read-only semiconductor memory comprising insulated gate field effect transistors and including a decoder matrix and a storage memory matrix, wherein said decoder matrix and said storage memory matrix each comprises intersecting rows and columns with each intersection defined by a single insulated gate field effect transistor; said decoder matrix including a. an interrogation input, b. a plurality of input circuits, c. each row of said decoder matrix including n-channel transistors having gates connected by a said input circuit to a respective corresponding address input, each said row transistor forming part of a different column of said decoder matrix and having a channel connected to the channel of the other transistors of said column, d. the channels of said transistors of a same column being connected by a common p-channel precharge transistor to a d.c. supply line, e. each said input circuit comprising a transfer gate including an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor, said n-channel transistor having a gate connected to an interrogation input, and a complementary conductivity type insulated gate field effect transistor inverter circuit connecting said interrogation input to a gate of said p-channel transistor of said transfer gate, and f. a decoder matrix output connected to each individual column thereof; said storage memory matrix including: 1. a read input, 2. a plurality of input circuit means for connecting respective column outputs of said decoder matrix to respective rows of said storage matrix,
Claim 8
Dependent Claim
78 words
each column of said storage memory matrix including a p-channel transistor having a channel connected between a common column conductor and a selected logic level voltage line, 4. means selectively connecting the gates of said p-channel transistors to row conductors of said storage memory matrix to define a predetermined read-only memory code, and 5. said p-channel transistors of a same column having their channels commonly connected with an n-channel insulated gate field effect load transistor for that column.
Claim 9
Dependent Claim
78 words
each column of said storage memory matrix including a p-channel transistor having a channel connected between a common column conductor and a selected logic level voltage line, 4. means selectively connecting the gates of said p-channel transistors to row conductors of said storage memory matrix to define a predetermined read-only memory code, and 5. said p-channel transistors of a same column having their channels commonly connected with an n-channel insulated gate field effect load transistor for that column.
Claim 10
Dependent Claim
35 words
A memory according to claim 5, wherein each column output of said decoder matrix includes a complementary conductivity type field effect transistor inverter circuit connecting with a corresponding row conductor of said storage memory matrix.
Claim 11
Dependent Claim
108 words
A memory according to claim 5, wherein said input circuit of each row of said storage memory matrix comprises a complementary conductivity type insulated gate field effect transistor transfer gate including an n-channel transistor and a p-channel transistor, said n-channel transistor having a gate connected to said read input of said storage memory matrix; and a complementary conductivity type field effect transistor inverter circuit connecting said read input to a gate of said p-channel transistor of said transfer gate and to the gates of said n-channel load transistors of each column of said storage memory matrix, said transfer gate being connected to a corresponding decoder matrix column output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |