Multi-functional arithmetic and logical unit

Claim 1

In a calculating system which includes data storage means for storing data which is to be arithmetically processed, and wherein arithmetic operations which can be effected by the calculating system are respectively defined by preselected combinations of binary bits in instruction words, an arithmetic logic unit comprising: logic control means for receiving each instruction and generating, responsive thereto, a discrete output enable signal corresponding to the arithmetic operation defined by said instruction; arithmetic logic means connected to receive said output enable signal, said arithmetic logic means including a plurality of logic gates selectively coupled to said storage means for accessing data stored therein, said arithmetic logic means for executing an arithmetic operation, the arithmetic logic means being responsive to said enable signal to effect the selected arithmetic operation on said data accessed from said storage means, said arithmetic logic means integrated on a single semiconductor chip adjacent said storage means and said logic control means, and selectively interconnected therewith by a single parallel bus system; and logic means for selectively connecting said storage means, said logic control means, and said arithmetic logic means to said bus system for controlling transmittal of data therebetween.