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US4035828A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: RCA Corp
•
Filing: 1976-05-21
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Granted: 1977-07-12
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Expires: 1996-05-21
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Abstract

Abstract A semiconductor integrated circuit device which may be utilized as a Darlington circuit having an input stage and an output stage is disclosed. The Darlington may be characterized as having an increased isolation between the input stage and the output stage.

Inventors

  • 👤 Willem Gerard Einthoven
  • 👤 Anthony Joseph Caravaggio
  • 👤 Albert Alexander Todd

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 20:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D84/641; H10D84/642; H10D88/00

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 211 words
A semiconductor device comprising: a body of semiconductor material having a surface and having a first region of a one type conductivity therein; a second region of semiconductor material having a second type conductivity and forming a first PN junction with said first region; a third region of semiconductor material having said one type conductivity adjacent said surface and forming a second PN junction with said second region, said third region being spaced apart from said first region by said second region; a plurality of fourth regions adjacent said surface, having said second type conductivity, within said third region and forming a plurality of third PN junctions therewith, a portion of said third region, comparatively thinner than the remainder thereof, being between each of said fourth regions and said second region, said comparatively thinner portion of said third region being about 2 μm thick and having an average impurity concentration on the order of about 10 15 atoms/cm 3 ; means defining a first electrode contacting a first member of said plurality of fourth regions; and means defining an interconnection electrode connecting a second member of said plurality of fourth regions to a first surface portion of said third region adjacent said surface between said first member and said second member.
Claim 2
Dependent Claim 211 words
A semiconductor device comprising: a body of semiconductor material having a surface and having a first region of a one type conductivity therein; a second region of semiconductor material having a second type conductivity and forming a first PN junction with said first region; a third region of semiconductor material having said one type conductivity adjacent said surface and forming a second PN junction with said second region, said third region being spaced apart from said first region by said second region; a plurality of fourth regions adjacent said surface, having said second type conductivity, within said third region and forming a plurality of third PN junctions therewith, a portion of said third region, comparatively thinner than the remainder thereof, being between each of said fourth regions and said second region, said comparatively thinner portion of said third region being about 2 μm thick and having an average impurity concentration on the order of about 10 15 atoms/cm 3 ; means defining a first electrode contacting a first member of said plurality of fourth regions; and means defining an interconnection electrode connecting a second member of said plurality of fourth regions to a first surface portion of said third region adjacent said surface between said first member and said second member.
Claim 3
Dependent Claim 49 words
A semiconductor device as claimed in claim 1 further comprising: means defining a second electrode contacting a second surface portion of said third region adjacent said surface, said second surface portion being spaced apart from said first surface portion by said second member of said fourth plurality of regions.
Claim 4
Dependent Claim 39 words
A semiconductor device as claimed in claim 2 wherein; said first region is comprised of at least laterally isolated portions, said laterally isolated portions being respectively positioned opposite said first and said second surface portions of said third region.
Claim 5
Dependent Claim 34 words
A semiconductor device as claimed in claim 1 wherein: said second member of said plurality of fourth regions substantially surrounds and is axially aligned with said first member of said plurality of fourth regions.
Claim 6
Dependent Claim 25 words
A semiconductor device as claimed in claim 1 wherein: said third region has comparatively shallower portions and comparatively deeper portions with respect to said surface.
Claim 7
Dependent Claim 64 words
A semiconductor device as claimed in claim 5 wherein: said third region has a surface impurity concentration of about 5× 10 20 atoms/cm 3 and an impurity concentration of about 5× 10 14 at said second PN junction in said comparatively deeper portion and an impurity concentration of about 5× 10 14 atoms/cm 3 at said second PN junction in said comparatively shallower portion.
Claim 8
Dependent Claim 24 words
A semiconductor device as claimed in claim 5 wherein: said plurality of fourth regions are in said comparatively shallower portion of said third region.

References Cited (Backward Citations)

US3671821A Cited
JPS4722430U Cited
US3836996A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-07-11 1981-01-10 1981-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-07-11 1985-01-10 1985-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-07-11 1989-01-10 1989-07-12 $7700.00 Window Closed / Lapsed

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