Patent US4035820A successfully refreshed from Google Patents.
US4035820A
Expired / Lapsed
US
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Adjustment of avalanche voltage in DIFMOS memory devices by control of impurity doping
Assignee: Texas Instruments Inc
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Filing: 1975-12-29
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Granted: 1977-07-12
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Expires: 1995-12-29
Abstract
Abstract A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.
Inventors
- 👤 Walter Theodore Matzen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:13
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/60; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
112 words
A semiconductor memory device having a monocrystalline semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate electron injection means in said substrate at least partially underlying said gate, hole injection means in said substrate spaced from said electron injector means and at least partially underlying said gate, and means for sensing the presence or absence of charge on said gate, wherein said electron injection means comprises an n+/p+ junction having a peak dopant concentration no greater than about 2× 10 17 cm - 3 on the n+ side, said n+ region having an implanted dopant profile, whereby peak dopant concentration is located beneath the semiconductor surface.
Claim 2
Dependent Claim
112 words
A semiconductor memory device having a monocrystalline semiconductor substrate of one conductivity type, an electrically isolated floating gate conductor overlying said substrate electron injection means in said substrate at least partially underlying said gate, hole injection means in said substrate spaced from said electron injector means and at least partially underlying said gate, and means for sensing the presence or absence of charge on said gate, wherein said electron injection means comprises an n+/p+ junction having a peak dopant concentration no greater than about 2× 10 17 cm - 3 on the n+ side, said n+ region having an implanted dopant profile, whereby peak dopant concentration is located beneath the semiconductor surface.
Claim 3
Dependent Claim
23 words
A device as in claim 1 wherein said n+/p+ junction comprises an n+ region having a peak dopant concentration of 10 17 atoms/cc.
Claim 4
Dependent Claim
40 words
A device as in claim 1 wherein said hole injection means comprises an n+p- junction, and a capacitor of which a portion of said gate is one plate, and a p- type region in said substrate is the other plate.
Claim 5
Dependent Claim
136 words
A semiconductor memory device comprising: (a) a monocrystalline semiconductor substrate of one conductivity type; (b) an adherent layer of insulating material covering one surface thereof; (c) an adherent electrically isolated floating gate conductor layer on said insulating material; (d) an n+p+ junction in said substrate for injecting electrons into and through said insulating layer for capture and storage on said gate, the n+ region thereof having a peak dopant concentration no greater than about 2× 10 17 cm - 3; said n+ region having an implanted dopant profile, whereby peak dopant concentration is located beneath the semiconductor surface; (e) means in said substate for injecting holes into and through said insulating layer for neutralizing stored charge in said gate; and (f) means in said substrate for sensing the presence or absence of charge in said gate.
Claim 6
Dependent Claim
136 words
A semiconductor memory device comprising: (a) a monocrystalline semiconductor substrate of one conductivity type; (b) an adherent layer of insulating material covering one surface thereof; (c) an adherent electrically isolated floating gate conductor layer on said insulating material; (d) an n+p+ junction in said substrate for injecting electrons into and through said insulating layer for capture and storage on said gate, the n+ region thereof having a peak dopant concentration no greater than about 2× 10 17 cm - 3; said n+ region having an implanted dopant profile, whereby peak dopant concentration is located beneath the semiconductor surface; (e) means in said substate for injecting holes into and through said insulating layer for neutralizing stored charge in said gate; and (f) means in said substrate for sensing the presence or absence of charge in said gate.
Claim 7
Dependent Claim
43 words
A device as in claim 4 wherein said hole injection means comprises an n+/p- junction in said substrate at least partially underlying said gate, and wherein the n+ region of said hole injection means overlaps the n+ region of said electron injection means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |