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US4035766A
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Error-checking scheme
Assignee: RTX BBN Technologies Corp
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Filing: 1975-08-01
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Granted: 1977-07-12
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Expires: 1995-08-01
Abstract
Abstract The error-checking scheme disclosed herein is adapted for use in digital data processing systems, e.g. computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address. In a preferred embodiment, the data is divided into two fields and a respective parity bit is generated corresponding to each data field. Each data parity bit is then combined with a parity bit corresponding to the binary address to yield a respective combinational parity bit. Each of the resultant combinational parity bits is then sourced with the respective data field. Accordingly, a system sub-component receiving the sourced data with the combinational parity bits can detect any type of single error occurring in either the address or the data.
Inventors
- 👤 William B. Barker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
In a digital data processing system having sub-components which source and receive digital data comprising at least one binary word and in which the data source or destination is designated by a binary address; the improvement comprising means for generating a parity signal, which means employs a logical array equivalent to: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D corresponding to at least a portion of the data word; means for generating and sourcing a parity bit AXD corresponding to the XOR product of A and D and also a second parity signal equivalent to AXD2 where A is the binary complement of A and D2 is a parity bit corresponding to at least part of the data word, whereby a sub-component receiving the sourced data can detect the most common errors in either address or data.
Claim 2
Dependent Claim
148 words
In a digital data processing system having sub-components which source and receive digital data comprising at least one binary word and in which the data source or destination is designated by a binary address; the improvement comprising means for generating a parity signal, which means employs a logical array equivalent to: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D corresponding to at least a portion of the data word; means for generating and sourcing a parity bit AXD corresponding to the XOR product of A and D and also a second parity signal equivalent to AXD2 where A is the binary complement of A and D2 is a parity bit corresponding to at least part of the data word, whereby a sub-component receiving the sourced data can detect the most common errors in either address or data.
Claim 3
Dependent Claim
22 words
A system as set fourth in claim 1 wherein D and D2 correspond to different and exclusive portions of the data word.
Claim 4
Dependent Claim
162 words
In a digital processing system having sub-components which source and receive digital data, in which the data comprises a binary word divisible into at least two fields and in which the data source or destination is designated by a binary address, the improvement comprising means for generating a pair of parity signals, which means employs a logical array equivalent to: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D1 corresponding to the first data field; means for generating a parity bit D2 corresponding to the second data field; means for generating and sourcing with the first data field a parity bit AXD1 corresponding to the XOR product of A and D1; and means for generating and sourcing with the second data field a parity bit AXD2 corresponding to the XOR product of A and D2, whereby a sub-component receiving the sourced data can detect most common errors in either address or data.
Claim 5
Dependent Claim
162 words
In a digital processing system having sub-components which source and receive digital data, in which the data comprises a binary word divisible into at least two fields and in which the data source or destination is designated by a binary address, the improvement comprising means for generating a pair of parity signals, which means employs a logical array equivalent to: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D1 corresponding to the first data field; means for generating a parity bit D2 corresponding to the second data field; means for generating and sourcing with the first data field a parity bit AXD1 corresponding to the XOR product of A and D1; and means for generating and sourcing with the second data field a parity bit AXD2 corresponding to the XOR product of A and D2, whereby a sub-component receiving the sourced data can detect most common errors in either address or data.
Claim 6
Dependent Claim
148 words
In a digital data processing system having sub-components which source and receive digital data, in which the data comprises a binary word divisible into at least two fields and in which the data source or destination is designated by a binary address; an error-checking scheme comprising: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D1 corresponding to the first data field; means for generating a parity bit D2 corresponding to the second data field; means for generating and sourcing with the first data field a parity bit AXD1 corresponding to the XOR product of A and D1; and means for generating and sourcing with the second data field a parity bit AXD2 corresponding to the XOR product of A and D2, whereby a sub-component receiving the sourced data can detect most common errors in either address or data.
Claim 7
Dependent Claim
148 words
In a digital data processing system having sub-components which source and receive digital data, in which the data comprises a binary word divisible into at least two fields and in which the data source or destination is designated by a binary address; an error-checking scheme comprising: means for generating a parity bit A corresponding to the binary address; means for generating a parity bit D1 corresponding to the first data field; means for generating a parity bit D2 corresponding to the second data field; means for generating and sourcing with the first data field a parity bit AXD1 corresponding to the XOR product of A and D1; and means for generating and sourcing with the second data field a parity bit AXD2 corresponding to the XOR product of A and D2, whereby a sub-component receiving the sourced data can detect most common errors in either address or data.
Claim 8
Dependent Claim
44 words
A system as set forth in claim 4 wherein said means for generating a parity bit AXD2 includes means for providing an additional complement whereby, if the data word is all binary ones or all binary zeros, the two parity bits will be complements.
References Cited (Backward Citations)
US3789204A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |