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US4034294A
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US
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Overlap PCM coder/decoder with reaction time compensation
Assignee: AT&T Inc
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Filing: 1976-05-19
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Granted: 1977-07-05
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Expires: 1996-05-19
Abstract
Abstract A PCM coder/decoder circuit is disclosed employing a counter that counts clock pulses until a transmitting ramp voltage equals that of an outgoing speech sample. The encoded count is transmitted in complemented form to the distant station where it is eventually entered into a counter similar to that of the transmitting station. Clock pulses are then applied to the receiving counter until a carry is generated at which time a receiving ramp waveform is disconnected from a decoding capacitor. The counter at the receiving station is enabled prematurely to generate the count so that the "reaction time" of the physical circuit components is compensated for. Compensation of this reaction time is important in reducing the nonlinear distortion that would otherwise be introduced when the ramp waveforms that are employed are of the companded type. The circuit operates in an overlap fashion, encoding and receiving in one field and decoding and transmitting in another field. Control time slots are interspersed between these fields and the control time slot intervals are advantageously employed to augment the code in the counter.
Inventors
- 👤 James Edwin Dalley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:34
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H03; H03M; H03M1/00; H03M1/02; H03M1/66; H03M1/82; H03M1/822; H03M1/827; H04J; H04J3/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/069
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
155 words
An arrangement for compensating both (a) for the time between the time of attainment of a predetermined count by a counter commencing to count clock pulses at an initial count determined by a received binary code pattern and the time a ramp signal is decoupled from a first analog signal storage device, and (b) for the time between the time said ramp signal equals the amplitude of a signal on a second analog signal storage device and the time said counter is disconnected from said clock pulses, comprising: means defining a sequence of successive field intervals during a first of which said ramp signal is connected and disconnected from said second analog signal storage device and during the second of which said clock pulses are coupled and decoupled from said counter; and means operative intermediate successive ones of said field intervals for augmenting by a predetermined amount, the count corresponding to said received code pattern.
Claim 2
Dependent Claim
155 words
An arrangement for compensating both (a) for the time between the time of attainment of a predetermined count by a counter commencing to count clock pulses at an initial count determined by a received binary code pattern and the time a ramp signal is decoupled from a first analog signal storage device, and (b) for the time between the time said ramp signal equals the amplitude of a signal on a second analog signal storage device and the time said counter is disconnected from said clock pulses, comprising: means defining a sequence of successive field intervals during a first of which said ramp signal is connected and disconnected from said second analog signal storage device and during the second of which said clock pulses are coupled and decoupled from said counter; and means operative intermediate successive ones of said field intervals for augmenting by a predetermined amount, the count corresponding to said received code pattern.
Claim 3
Dependent Claim
61 words
An arrangement according to claim 1 wherein said means operative intermediate said successive field intervals comprises: register means having received therein said binary code pattern during said first of said successive field intervals; and means for interchanging the contents of said register means with the contents accruing in said counter prior to said augmenting of said count by said predetermined amount.
Claim 4
Dependent Claim
43 words
The arrangement of claim 2 wherein said means defining said sequence of successive field intervals includes means defining a first control interval intermediate said first and said second successive field intervals and a second control interval following said second of said field intervals.
Claim 5
Dependent Claim
38 words
The arrangement of claim 3 further comprising means defining a first portion of one of said control intervals for enabling said contents interchanging means and a second portion of said same control interval for enabling said augmenting means.
Claim 6
Dependent Claim
66 words
The arrangement according to claim 4 further comprising means for loading said register means with a binary zero incident to transmitting each bit of the binary code pattern thereof to a remote point; and means operative during said second of said control intervals for again interchanging the contents of said register means and said counter to reset said counter after said code pattern has been transmitted.
Claim 7
Dependent Claim
128 words
A pulse code modulation system comprising: means for generating a binary pattern approximating the instant within a counting interval at which a companded ramp waveform and an analog sample correspond; means for receiving said binary pattern at a decoder; means associated with said decoder for connecting a second companded ramp waveform to an analog signal storage device throughout an interval of time measured by clock pulses, said interval of time being approximated by the number of clock pulses constituting a translation of said binary code pattern; and means for compensating for the degree of said first and second mentioned approximations due to the reaction time in detecting said instant and said interval including means for altering said binary pattern prior to connecting said waveform to said storage device.
Claim 8
Dependent Claim
128 words
A pulse code modulation system comprising: means for generating a binary pattern approximating the instant within a counting interval at which a companded ramp waveform and an analog sample correspond; means for receiving said binary pattern at a decoder; means associated with said decoder for connecting a second companded ramp waveform to an analog signal storage device throughout an interval of time measured by clock pulses, said interval of time being approximated by the number of clock pulses constituting a translation of said binary code pattern; and means for compensating for the degree of said first and second mentioned approximations due to the reaction time in detecting said instant and said interval including means for altering said binary pattern prior to connecting said waveform to said storage device.
Claim 9
Dependent Claim
124 words
A circuit for decoding a binary code pattern into an analog signal comprising: means defining a sequence of successive field intervals and shorter duration control time slots intermediate successive ones of said field intervals; register means operative during a first one of said field intervals for receiving said binary pattern; counter means; means operative during one portion of a succeeding one of said control intervals for transferring said received binary pattern to said counter; means operative during another portion of said one of said control intervals for augmenting the contents of said counter by a predetermined amount; and means operative during a subsequent one of said field intervals for measuring the interval of time required to cause said counter to attain a predetermined count.
Claim 10
Dependent Claim
124 words
A circuit for decoding a binary code pattern into an analog signal comprising: means defining a sequence of successive field intervals and shorter duration control time slots intermediate successive ones of said field intervals; register means operative during a first one of said field intervals for receiving said binary pattern; counter means; means operative during one portion of a succeeding one of said control intervals for transferring said received binary pattern to said counter; means operative during another portion of said one of said control intervals for augmenting the contents of said counter by a predetermined amount; and means operative during a subsequent one of said field intervals for measuring the interval of time required to cause said counter to attain a predetermined count.
Claim 11
Dependent Claim
97 words
In a circuit for coupling a companded ramp signal source to a sampling capacitor for an interval of time determined by a code pattern registered in a counter, the improvement comprising: means for transferring said pattern into said counter during a first interval of time; means for artificially augmenting said count by a predetermined amount during a second interval of time; and means thereafter operative to couple a source of time-interval-defining clock pulses to said counter until said predetermined count is attained, said predetermined amount of count augmenting corresponding to an ascertainable number of said clock pulses.
Claim 12
Dependent Claim
97 words
In a circuit for coupling a companded ramp signal source to a sampling capacitor for an interval of time determined by a code pattern registered in a counter, the improvement comprising: means for transferring said pattern into said counter during a first interval of time; means for artificially augmenting said count by a predetermined amount during a second interval of time; and means thereafter operative to couple a source of time-interval-defining clock pulses to said counter until said predetermined count is attained, said predetermined amount of count augmenting corresponding to an ascertainable number of said clock pulses.
Claim 13
Dependent Claim
89 words
In a PCM coder/decoder arrangement for a communication switching system, the combination comprising: a counter for receiving an input PCM signal from a local station; a shift register for receiving a PCM signal from a remote station; means for interchanging the contents of said counter and said shift register; means for augmenting the count of said counter by a predetermined amount above the contents interchanged from said shift register; and means responsive to a carry signal from said counter for transferring to the local station an analog speech signal.
Claim 14
Dependent Claim
89 words
In a PCM coder/decoder arrangement for a communication switching system, the combination comprising: a counter for receiving an input PCM signal from a local station; a shift register for receiving a PCM signal from a remote station; means for interchanging the contents of said counter and said shift register; means for augmenting the count of said counter by a predetermined amount above the contents interchanged from said shift register; and means responsive to a carry signal from said counter for transferring to the local station an analog speech signal.
Claim 15
Dependent Claim
40 words
In a PCM coder/decoder arrangement, the combination in accordance with claim 9 further comprising means responsive to the comparison of a companded ramp signal and the amplitude of a speech signal for applying said input PCM signal to said counter.
Claim 16
Dependent Claim
39 words
In a PCM coder/decoder arrangement, the combination in accordance with claim 10 wherein said transferring means includes means for generating a receiving ramp signal and means responsive to said carry signal for said controlling receiving ramp signal generating means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-04 | 1981-01-03 | 1981-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-04 | 1985-01-03 | 1985-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-04 | 1989-01-03 | 1989-07-05 | $7700.00 | Window Closed / Lapsed |