US3931531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Overlapped signal transition counter
Assignee: International Business Machines Corp
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Filing: 1974-12-17
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Granted: 1976-01-06
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Expires: 1994-12-17
Abstract
Abstract A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.
Inventors
- 👤 Glenn P. Check
- 👤 Roger F. Dimmick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:09
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; G; G06; G06K; G06K15/00; G06K15/02; G06K15/16
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
107 words
A counter circuit for counting signal transitions of overlapped out of phase bi-level signals in response to an asynchronously occurring start signal comprising means responsive to said overlapped out of phase bi-level signals for generating a single signal having signal transitions for every signal transition, positive and negative, occurring within said overlapped signals, means responsive to said start signal for storing the level of said single signal at the time said start signal occurs, binary counter means, and logic means responsive to said single signal and said stored level to provide counter advance signals to said binary counter means for each signal transition in said single signal.
Claim 2
Dependent Claim
107 words
A counter circuit for counting signal transitions of overlapped out of phase bi-level signals in response to an asynchronously occurring start signal comprising means responsive to said overlapped out of phase bi-level signals for generating a single signal having signal transitions for every signal transition, positive and negative, occurring within said overlapped signals, means responsive to said start signal for storing the level of said single signal at the time said start signal occurs, binary counter means, and logic means responsive to said single signal and said stored level to provide counter advance signals to said binary counter means for each signal transition in said single signal.
Claim 3
Dependent Claim
31 words
The counter circuit of claim 1 wherein said means for generating a single signal having signal transitions for every signal transition occurring within said overlapped signals is logical exclusive OR circuitry.
Claim 4
Dependent Claim
139 words
The counter circuit of claim 2 wherein said logical exclusive OR circuitry comprises a first AND circuit connected to receive said overlapped out of phase bi-level signals, a second AND circuit connected to the output of said first AND circuit and connected to receive one of said out of phase bi-level signals, a third AND circuit connected to the output of said first AND circuit and connected to receive another of said out of phase bi-level signals, and an OR circuit connected to the outputs of said second and third AND circuits to provide an output at one level when the outputs of said second and third AND circuits are at levels different from each other and to provide an output at another level when the outputs of said second and third AND circuits are at the same level.
Claim 5
Dependent Claim
29 words
The counter circuit of claim 1 wherein said means for storing the level of said single signal at the time said start signal occurs is a polarity hold circuit.
Claim 6
Dependent Claim
97 words
The counter circuit of claim 4 wherein said polarity hold circuit comprises a first AND circuit connected to receive said single signal and said start signal, inverter means for inverting said single signal, a second AND circuit connected to receive said inverted single signal and said start signal, and a pair of OR circuits connected to each other to form a latch and connected to outputs of said first and second AND circuits whereby the level of said single signal is stored upon the occurrence of said start signal in the latch formed by said OR circuits.
Claim 7
Dependent Claim
30 words
The counter circuit of claim 1 wherein said logic means for providing said counter advance signals to said binary counter means forms the first stage of said binary counter means.
Claim 8
Dependent Claim
83 words
The counter circuit of claim 1 wherein said logic means for providing counter advance signals comprises a first AND circuit connected to receive said stored level, said single signal in inverted form and said start signal, a second AND circuit connected to receive said stored level, said single signal and said start signal, and an OR circuit connected to outputs of said first and second AND circuits to provide counter output signals for both negative and positive transitions occurring in said single signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-05 | 1979-07-07 | 1980-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-05 | 1983-07-07 | 1984-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-05 | 1987-07-07 | 1988-01-06 | $7700.00 | Window Closed / Lapsed |