Patent US4032768A successfully refreshed from Google Patents.
US4032768A
Expired / Lapsed
US
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Constant velocity vector generator
Assignee: Tektronix Inc
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Filing: 1975-10-24
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Granted: 1977-06-28
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Expires: 1995-10-24
Abstract
Abstract A Constant Velocity Vector Generator is disclosed for connecting X, Y coordinate points of a rectangular coordinate display system. Simultaneous ΔX and ΔY step voltages are converted to ramp voltage pairs which are applied to appropriate X and Y deflection circuits of a graphic display device to produce straight-line traces whose velocities are constant for all vectors regardless of magnitude (line length) or direction (angle). Each vector may be drawn to any length or direction, immediately after which new data may be applied to the vector generator to initiate a new vector whose origin is the end point of the preceding vector. Such a system is particularly applicable to computer-drawn displays. The vector generating circuits are suitable for realization in a monolithic integrated circuit.
Inventors
- 👤 Michael Lawrence Rieger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:21
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/22
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
112 words
A system for converting a pair of substantially simultaneous step voltages to a pair of linear ramp voltages at a constant rate, comprising: means for comparing said pair of step voltages to said ramp voltages and producing a pair of difference currents i a and i b therefrom; means responsive to said difference currents for producing a current i c which may be defined mathematically as √ i a 2 + i b 2 ; means for producing a pair of substantially constant currents which may be defined mathematically as i a /i c and i b /i c respectively; and means for integrating said constant currents to produce said ramp voltages.
Claim 2
Independent Claim
112 words
A system for converting a pair of substantially simultaneous step voltages to a pair of linear ramp voltages at a constant rate, comprising: means for comparing said pair of step voltages to said ramp voltages and producing a pair of difference currents i a and i b therefrom; means responsive to said difference currents for producing a current i c which may be defined mathematically as √ i a 2 + i b 2 ; means for producing a pair of substantially constant currents which may be defined mathematically as i a /i c and i b /i c respectively; and means for integrating said constant currents to produce said ramp voltages.
Claim 3
Independent Claim
113 words
A system for generating vectors which are drawn at a substantially constant velocity between data points of a rectangular coordinate display, comprising: input means for iteratively receiving voltage levels corresponding to data points of said display and generating first error signals in pairs proportional to ΔX and ΔY vector components; means for combining said first error signals to produce combined second error signals proportional to the magnitudes of said vectors; means for dividing said first error signals by said second error signals for iteratively producing pairs of substantially constant currents; and means for integrating said pairs of currents to produce X and Y deflection signals which are substantially linear between said data points.
Claim 4
Independent Claim
113 words
A system for generating vectors which are drawn at a substantially constant velocity between data points of a rectangular coordinate display, comprising: input means for iteratively receiving voltage levels corresponding to data points of said display and generating first error signals in pairs proportional to ΔX and ΔY vector components; means for combining said first error signals to produce combined second error signals proportional to the magnitudes of said vectors; means for dividing said first error signals by said second error signals for iteratively producing pairs of substantially constant currents; and means for integrating said pairs of currents to produce X and Y deflection signals which are substantially linear between said data points.
Claim 5
Dependent Claim
28 words
A system according to claim 2 wherein said input means includes absolute value circuit means responsive to bipolar input voltage levels for producing unipolar first error signals therefrom.
Claim 6
Dependent Claim
19 words
A system according to claim 2 wherein said means for combining said first error signals includes a square-root-of-the-sum-of-the-squares circuit.
Claim 7
Dependent Claim
24 words
A system according to claim 2 further including means responsive to said second error signals for producing indicating signals during production of said vectors.
Claim 8
Dependent Claim
28 words
A system according to claim 2 further including fast-slew means for causing said X and Y deflection signals to track non-linearly with changes in said input voltage levels.
Claim 9
Dependent Claim
43 words
A system according to claim 6 wherein said fast-slew means includes switch means for disconnecting said second error signals from said divider means so that said divider means produces pairs of current impulses in response to step changes in said input voltage levels.
Claim 10
Dependent Claim
148 words
In an apparatus for displaying graphical information utilizing rectangular coordinates having X and Y axes, said apparatus including a writing element and X and Y deflection circuits for positioning said element, a vector generating system for connecting data points of said display, comprising: means for generating pairs of voltage levels defining the X and Y coordinates respectively of a display; means for comparing said pairs of voltage levels to the X and Y outputs of said system and generating therefrom ΔX and ΔY error signals; means for squaring said ΔX and ΔY error signals, summing the squares and taking the square root thereof to produce ΔR error signals; means for generating a pair of currents having values proportional to ΔX/ΔR and ΔY/ΔR respectively; and means for integrating said respective currents to produce X and Y deflection signal outputs to be provided to said X and Y deflection circuits.
Claim 11
Dependent Claim
148 words
In an apparatus for displaying graphical information utilizing rectangular coordinates having X and Y axes, said apparatus including a writing element and X and Y deflection circuits for positioning said element, a vector generating system for connecting data points of said display, comprising: means for generating pairs of voltage levels defining the X and Y coordinates respectively of a display; means for comparing said pairs of voltage levels to the X and Y outputs of said system and generating therefrom ΔX and ΔY error signals; means for squaring said ΔX and ΔY error signals, summing the squares and taking the square root thereof to produce ΔR error signals; means for generating a pair of currents having values proportional to ΔX/ΔR and ΔY/ΔR respectively; and means for integrating said respective currents to produce X and Y deflection signal outputs to be provided to said X and Y deflection circuits.
Claim 12
Dependent Claim
26 words
A vector generating system in accordance with claim 8 further including means for generating a square-wave pulse coincident with the duration of said ΔR error signals.
Claim 13
Dependent Claim
53 words
A vector generating system in accordance with claim 8 further including fast-slew means for quickly positioning said writing element, said fast slew means including switch means for disconnecting said ΔR error signals from said current generating means to substantially increase said generated currents when said ΔX and ΔY error signals are received thereby.
Claim 14
Dependent Claim
65 words
A vector generating system in accordance with claim 8 wherein said integrating means includes a pair of operational amplifiers, each of said operational amplifiers having a capacitor in the feedback circuit thereof, wherein the rate of change of X and Y deflection voltages from one data point to another is dependent upon the values of said capacitors and the quantity of said generated currents thereinto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-27 | 1980-12-27 | 1981-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-27 | 1984-12-27 | 1985-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-27 | 1988-12-27 | 1989-06-28 | $7700.00 | Window Closed / Lapsed |