US3725897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Visual display system
Assignee: Raytheon Co
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Filing: 1971-01-20
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Granted: 1973-04-03
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Expires: 1991-01-20
Abstract
Abstract A constant writing rate vector generator capable of accepting digital inputs representative of the endpoints of a line and converting them into analog voltages proportional to the transition time of the generated line such that random positioning of the electron beam on a cathode ray tube and the writing of vectors while maintaining an equal and constant brightness without additional intensity compensation is achieved. The digital endpoint data controls a constant voltage ramp with a time duration directly proportional to the vector length, which ramp is used to control the transition rate of a pair of digital to analog converters.
Inventors
- 👤 M Bleiweiss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:53
CPC Classifications
G; G09; G09G; G09G1/00; G09G1/06; G09G1/08; G09G1/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
375 words
A visual display system comprising: means for generating digital vector end point data; means for converting said digital data to analog signals having a time duration that is directly proportional to the length of said vector; means coupled to said converting means for generating a visual display at a constant writing rate; means coupled to said means for generating digital vector end point data for generating stroke length data; means for generating a voltage ramp with a time duration directly proportional to said derived stroke length; means for switching said voltage ramp into said digital-toanalog converting means in accordance with said digital end point data such that a constant transition rate vector is generated on said visual display; and wherein said means for generating stroke length data comprises a hypotenuse approximation circuit which comprises: a first subtractor for subtracting the X component of a starting point of said vector from the X component of an end point of said vector; a second subtractor for subtracting the Y component of a starting point of said vector from the Y component of an end point of said vector; a comparator for comparing the outputs of said first and said second subtractors; first combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said first subtractor with one-half the output of said second subtractor when the output of said second subtractor is greater than the output of said first subtractor; second combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said second subtractor with one-half the output of said first subtractor when the output of said first subtractor is greater than the output of said second subtractor; and means for coupling the output of said first combining means and the output of said second combining means to said ramp generating means, the output of said first combining means being the hypotenuse approximation when the output of said second subtractor is greater than the output of said first subtractor, the output of said second combining means being the hypotenuse approximation when the output of said first subtractor is greater than the output oF said second subtractor.
Claim 2
Dependent Claim
375 words
A visual display system comprising: means for generating digital vector end point data; means for converting said digital data to analog signals having a time duration that is directly proportional to the length of said vector; means coupled to said converting means for generating a visual display at a constant writing rate; means coupled to said means for generating digital vector end point data for generating stroke length data; means for generating a voltage ramp with a time duration directly proportional to said derived stroke length; means for switching said voltage ramp into said digital-toanalog converting means in accordance with said digital end point data such that a constant transition rate vector is generated on said visual display; and wherein said means for generating stroke length data comprises a hypotenuse approximation circuit which comprises: a first subtractor for subtracting the X component of a starting point of said vector from the X component of an end point of said vector; a second subtractor for subtracting the Y component of a starting point of said vector from the Y component of an end point of said vector; a comparator for comparing the outputs of said first and said second subtractors; first combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said first subtractor with one-half the output of said second subtractor when the output of said second subtractor is greater than the output of said first subtractor; second combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said second subtractor with one-half the output of said first subtractor when the output of said first subtractor is greater than the output of said second subtractor; and means for coupling the output of said first combining means and the output of said second combining means to said ramp generating means, the output of said first combining means being the hypotenuse approximation when the output of said second subtractor is greater than the output of said first subtractor, the output of said second combining means being the hypotenuse approximation when the output of said first subtractor is greater than the output oF said second subtractor.
Claim 3
Dependent Claim
358 words
A vector generator comprising: means for receiving digital vector end point data; means for converting said digital end point data into a digital quantity representative of the vector length; means for generating control voltages responsive to said digital quantity, the time duration of said control voltages being proportional to the vector length; digital-to-analog means for converting said control voltages to analog signals in accordance with said digital end point data; means for displaying said analog signals as vectors at a constant writing rate; said means for receiving digital vector end point data comprising first and second storage registers for receiving vector starting point data and vector end point data for a first axis, said vector end point receiving means further comprising third and fourth storage registers for receiving vector starting point data and vector end point data for a second axis, said second axis being orthogonal to said first axis; said means for converting said digital end point data into a digital quantity representative of said vector length comprising: means for digitally approximating the function Square Root ( Delta X)2 + ( Delta Y)2 substituting therefor the quantity Delta X + 1/2 Delta Y when Delta X > Delta Y and Delta Y + 1/2 Delta X when Delta Y > or = Delta X where Delta X is the absolute value of the difference between the vector end point and starting point in the X axis and Delta Y is the difference between the vector end point and starting point in the Y axis; and wherein said digital approximation means includes: first and second subtractors for deriving the quantities Delta X and Delta Y, from said first and second and said third and fourth storage registers, respectively; a comparator for comparing the outputs of said first and second subtractors; first means for storing the output of said comparator when Delta Y > or = Delta X; second means for storing the output of said comparator when Delta X > or = Delta Y; means for adding the outputs of said first and second storage registers to derive said digital approximation; and means for storing said digital approximation.
Claim 4
Dependent Claim
358 words
A vector generator comprising: means for receiving digital vector end point data; means for converting said digital end point data into a digital quantity representative of the vector length; means for generating control voltages responsive to said digital quantity, the time duration of said control voltages being proportional to the vector length; digital-to-analog means for converting said control voltages to analog signals in accordance with said digital end point data; means for displaying said analog signals as vectors at a constant writing rate; said means for receiving digital vector end point data comprising first and second storage registers for receiving vector starting point data and vector end point data for a first axis, said vector end point receiving means further comprising third and fourth storage registers for receiving vector starting point data and vector end point data for a second axis, said second axis being orthogonal to said first axis; said means for converting said digital end point data into a digital quantity representative of said vector length comprising: means for digitally approximating the function Square Root ( Delta X)2 + ( Delta Y)2 substituting therefor the quantity Delta X + 1/2 Delta Y when Delta X > Delta Y and Delta Y + 1/2 Delta X when Delta Y > or = Delta X where Delta X is the absolute value of the difference between the vector end point and starting point in the X axis and Delta Y is the difference between the vector end point and starting point in the Y axis; and wherein said digital approximation means includes: first and second subtractors for deriving the quantities Delta X and Delta Y, from said first and second and said third and fourth storage registers, respectively; a comparator for comparing the outputs of said first and second subtractors; first means for storing the output of said comparator when Delta Y > or = Delta X; second means for storing the output of said comparator when Delta X > or = Delta Y; means for adding the outputs of said first and second storage registers to derive said digital approximation; and means for storing said digital approximation.
Claim 5
Dependent Claim
274 words
In combination: means for receiving components of data of a vector to be displayed, said data having an X component and a Y component of a start point of said vector, and said data having an X component and a Y component of an end point of said vector; means for generating a ramp signal, said ramp generating means including means for inverting said ramp signal; means coupled to said data receiving means and said ramp generation means for multiplying said start point data and said end point data by respectively said inverted ramp signal and said ramp signal; means coupled to said multiplying means for combining output signals of said multiplying means for displaying said vector; a hypotenuse approximation circuit coupled to said ramp generation means for varying the rate of change of said ramp signal, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X and said Y component of said start point and said X and Y component of said end point; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.
Claim 6
Dependent Claim
274 words
In combination: means for receiving components of data of a vector to be displayed, said data having an X component and a Y component of a start point of said vector, and said data having an X component and a Y component of an end point of said vector; means for generating a ramp signal, said ramp generating means including means for inverting said ramp signal; means coupled to said data receiving means and said ramp generation means for multiplying said start point data and said end point data by respectively said inverted ramp signal and said ramp signal; means coupled to said multiplying means for combining output signals of said multiplying means for displaying said vector; a hypotenuse approximation circuit coupled to said ramp generation means for varying the rate of change of said ramp signal, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X and said Y component of said start point and said X and Y component of said end point; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.
Claim 7
Dependent Claim
198 words
In a system employing a ramp generator for generating a display of vectors each of which are drawn from a start point to an end point, the start point and the end point each being described by an X component and a Y component, a hypotenuse approximation circuit coupled to the ramp generator for varying the rate of change of ramp signals provided by said ramp generator, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X components and said Y components of said start and said end points; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.
Claim 8
Dependent Claim
198 words
In a system employing a ramp generator for generating a display of vectors each of which are drawn from a start point to an end point, the start point and the end point each being described by an X component and a Y component, a hypotenuse approximation circuit coupled to the ramp generator for varying the rate of change of ramp signals provided by said ramp generator, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X components and said Y components of said start and said end points; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-02 | 1976-10-02 | 1977-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-02 | 1980-10-02 | 1981-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-02 | 1984-10-02 | 1985-04-03 | $7700.00 | Window Closed / Lapsed |