US4031380A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and device for the integration of analog signals
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1975-09-15
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Granted: 1977-06-21
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Expires: 1995-09-15
Abstract
Abstract In a method and a device for storing analog signals in integrated circuit elements, the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor. After discrete sampling of the analog signal has been performed at N points, the N amplitudes corresponding to the N points are stored in N transistors in the form of a threshold voltage.
Inventors
- 👤 Luc Audaire
- 👤 Joseph Borel
- 👤 Vincent LE Goascoz
- 👤 Robert Poujois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:04
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/005; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163; G06G7/19; G06G7/1907
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
123 words
A method of integration of an analog signal in integrated circuit memory elements, wherein the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor, comprising the steps of performing a discrete sampling of the analog signal at N points, storing the N amplitudes corresponding to the N points in the form of threshold voltages in N of said transistors, then storing the amplitudes corresponding to N points of successive sampling of the analog signal in one transistor by successively adding those amplitudes to the threshold voltage of said one transistor, and reading the resultant threshold voltage of said one transistor as the result of the integration.
Claim 2
Independent Claim
123 words
A method of integration of an analog signal in integrated circuit memory elements, wherein the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor, comprising the steps of performing a discrete sampling of the analog signal at N points, storing the N amplitudes corresponding to the N points in the form of threshold voltages in N of said transistors, then storing the amplitudes corresponding to N points of successive sampling of the analog signal in one transistor by successively adding those amplitudes to the threshold voltage of said one transistor, and reading the resultant threshold voltage of said one transistor as the result of the integration.
Claim 3
Dependent Claim
19 words
A method according to claim 1, wherein the transistors which constitute the memory elements are of the metal-insulator-insulator-semiconductor type.
Claim 4
Dependent Claim
32 words
A method according to claim 1, further comprising applying a calibrated pulse to the transistor gates for zero resetting of the memory elements prior to applying a writing voltage to said gates.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |