Patent US4030073A successfully refreshed from Google Patents.
US4030073A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Initialization circuit for establishing initial operation of a digital computer
Assignee: Digital Equipment Corp
•
Filing: 1975-11-05
•
Granted: 1977-06-14
•
Expires: 1995-11-05
Abstract
Abstract A circuit for initializing a digital computer. Whenever an operator turns on a power supply for the digital computer or activates a console switch, the circuit transmits overriding address signals. These signals divert the digital computer from a normal initializing routine to a routine provided by the initializing circuit. The routine in the initializing circuit includes digital computer instruction sequences for performing preliminary diagnostic operations and for transferring instructions to a main memory from preselected peripherals. When the routine is complete, the computer is prepared to process other programs and to operate with other peripherals.
Inventors
- 👤 Robert A. Armstrong, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
259 words
An initialization circuit for loading initial information including data and instructions defining a predetermined operating condition into a digital computer system that includes a bus, a power supply, first means for transmitting address signals onto the bus when the power supply initially is energized, means for transmitting a power supply status signal onto the bus and means for transmitting and receiving transfer control signals onto and from the bus to transfer information over the bus, said initialization circuit comprising: A. memory means including a storage location containing the initial information and instructions for loading the initial information onto the bus for transfer to the digital computer system, B. address generator means for transmitting address signals onto the bus, and C. control means connected to the bus, said address generator means and said memory means for controlling transfers of information from said memory means, said control means including: i. means responsive to the power supply status signal from the bus for enabling said address generator means to transmit address signals onto the bus simultaneously with the transmission of address signals from the first address signal transmitting means in the digital computer system thereby to produce combined address signals that designate a said storage location in said memory means, and ii. transfer means responsive to certain of the control signals and the combined address signals on the bus for transferring the contents of said storage location in said memory means over the bus to the digital computer system thereby to establish the predetermined initial operating condition in the digital computer system.
Claim 2
Dependent Claim
259 words
An initialization circuit for loading initial information including data and instructions defining a predetermined operating condition into a digital computer system that includes a bus, a power supply, first means for transmitting address signals onto the bus when the power supply initially is energized, means for transmitting a power supply status signal onto the bus and means for transmitting and receiving transfer control signals onto and from the bus to transfer information over the bus, said initialization circuit comprising: A. memory means including a storage location containing the initial information and instructions for loading the initial information onto the bus for transfer to the digital computer system, B. address generator means for transmitting address signals onto the bus, and C. control means connected to the bus, said address generator means and said memory means for controlling transfers of information from said memory means, said control means including: i. means responsive to the power supply status signal from the bus for enabling said address generator means to transmit address signals onto the bus simultaneously with the transmission of address signals from the first address signal transmitting means in the digital computer system thereby to produce combined address signals that designate a said storage location in said memory means, and ii. transfer means responsive to certain of the control signals and the combined address signals on the bus for transferring the contents of said storage location in said memory means over the bus to the digital computer system thereby to establish the predetermined initial operating condition in the digital computer system.
Claim 3
Dependent Claim
155 words
An initialization circuit as recited in claim 1 wherein the digital computer system includes means for transmitting, as certain of the transfer control signals, signals designating a reading operation during the time the contents of one of said storage locations identified by address signals on the bus are transferred to the digital computer system and wherein: A. said memory means includes a plurality of said storage locations, each said storage location having an identifying address, B. said transfer means includes: a. an address decoder for generating a valid address signal whenever the address signals on the bus correspond to the address for one of said storage locations in said memory means and certain of the control signals designate a reading operation, and b. transfer control means responsive to the valid address signal from said address decoder for transferring the contents of the addressed one of said storage locations in said memory means onto the bus.
Claim 4
Dependent Claim
72 words
An initialization circuit as recited in claim 2 wherein said memory means comprises: i. a read-only memory responsive to the address signals from the bus for generating signals representing the contents of the addressed one of said storage locations, and ii. gating means connected to said read-only memory and to said control means for coupling the contents of the addressed one of said storage locations in said read-only memory onto the bus.
Claim 5
Dependent Claim
98 words
An initialization circuit as recited in claim 3 wherein: i. said gating means includes, for each of a plurality of preselected signals from said read-only memory, a. switch-operated enabling means for generating an enabling signal, and b. gating means responsive to a signal from said control means, a corresponding signal from the read-only memory and the enabling signal from said switch-operated enabling means, and ii. said address decoder includes means responsive to a predetermined address for energizing each said enabling means thereby to load a signal onto the bus which overrides the corresponding signal from said read-only memory.
Claim 6
Dependent Claim
51 words
An initialization circuit as recited in claim 1 additionally comprising: E. means for transmitting an overriding power supply status signal whereby said address generator enabling means causes an overriding address signal to be transmitted onto the bus, and F. switch means for energizing said overriding power supply status signal transmitting means.
References Cited (Backward Citations)
US3321747A
Cited
US3470538A
Cited
US3535560A
Cited
US3517171A
Cited
US3736569A
Cited
US3909790A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-13 | 1980-12-13 | 1981-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-13 | 1984-12-13 | 1985-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-13 | 1988-12-13 | 1989-06-14 | $7700.00 | Window Closed / Lapsed |