Low-crosstalk-automatic resetting scheme for Josephson junction logic circuit

Claim 2

A Josephson array comprising at least two Josephson junctions connected in series in a line adapted to carry current to said junctions, said junctions generating transients due to switching, said line including means disposed between said two junctions for substantially preventing said transients from passing between said two junctions.

Claim 3

A Josephson array as claimed in claim 1 wherein said last mentioned means is a characteristic impedance mismatch in said line.

Claim 4

A Josephson array as claimed in claim 1 wherein said means for reducing comprises first, second and third sections of said line having relatively high, low and high, respectively, characteristic impedances, said first section connected at one end to one of said junctions and at the other end to one end of said second section, the other end of said second section connected to one end of said third section, the other end of said third section connected to said other junction.

Claim 5

The array of claim 1, where said line is comprised of a superconductive material.

Claim 6

A Josephson array comprising a superconducting ground plane, an insulator layer overlaying said ground plane, a plurality of feeder line superconducting paths overlapping one another with tunnelling barriers therebetween forming a feeder line superconductor with a plurality of Josephson tunnelling junctions connected in series in said feeder line, output circuit paths connected in parallel with said junctions and comprising superconducting output lines, control lines adjacent to said junctions, said feeder line superconducting paths forming a transmission line with said ground plane and said insulating layer, said feeder line superconducting paths between any two of said series connected junctions comprising two characteristic impedance mismatches.

Claim 7

A Josephson array comprising a superconducting ground plane, an insulator layer overlaying said ground plane, a plurality of feeder line superconducting paths overlapping one another with tunnelling barriers therebetween forming a feeder line superconductor with a plurality of Josephson tunnelling junctions connected in series in said feeder line, output circuit paths connected in parallel with said junctions and comprising superconducting output lines, control lines adjacent to said junctions, said feeder line superconducting paths forming a transmission line with said ground plane and said insulating layer, said feeder line superconducting paths between any two of said series connected junctions comprising two characteristic impedance mismatches.

Claim 8

A Josephson array as claimed in claim 5 wherein said feeder line superconducting paths between any two of said series connected junctions consists of three sections formed in series between the said two junctions, the first and third sections, which contact said two junctions, respectively, have substantially equal characteristic impedances, and the second section, which joins said first and third sections, having a characteristic impedance substantially less than said equal characteristic impedances.

Claim 9

A Josephson array as claimed in claim 6 wherein the impedance mismatch between said first and second, and said second and third sections, is great enough to cause substantially all of a transient current caused by either junction switching to a finite voltage state to be reflected at the mismatch interfaces between said section and enable self-resetting of the switched junction.

Claim 10

A Josephson junction as claimed in claim 7 wherein said superconducting output lines form transmission lines with said ground plane and said insulator layer, said latter transmission lines having a characteristic impedance intermediate the characteristic impedances of said first and second sections.

Claim 11

A Josephson junction array comprising at least two Josephson junctions connected in series, said junctions generating transients due to switching, and means disposed between said two junctions for substantially preventing said transients from passing between said two junctions.

Claim 12

A Josephson junction array comprising at least two Josephson junctions connected in series, said junctions generating transients due to switching, and means disposed between said two junctions for substantially preventing said transients from passing between said two junctions.

Claim 13

A Josephson junction array as claimed in claim 9 wherein said means for reducing cross-talk comprises means for causing reflection in the series connection of said two junctions of a transient signal which is caused when one of said junctions switches from a zero voltage state to a finite voltage state.

Claim 14

A Josephson junction circuit comprising at least a single Josephson junction adapted for switching from the zero voltage state to a finite voltage state, said switching producing at least a single current pulse transient, a current source, and means disposed in series with said junction and said source for containing said at least a single current pulse transient to the location of said single Josephson junction.

Claim 15

A Josephson junction circuit comprising at least a single Josephson junction adapted for switching from the zero voltage state to a finite voltage state, said switching producing at least a single current pulse transient, a current source, and means disposed in series with said junction and said source for containing said at least a single current pulse transient to the location of said single Josephson junction.

Claim 16

A Josephson junction circuit as claimed in claim 11 wherein said means for containing comprises means disposed in series with said junction for providing an impedance mismatch to said current pulse transient.

Claim 17

A Josephson junction circuit comprising a current source, at least a single latching Josephson junction adapted for switching from a zero voltage state to a finite voltage state connected to said source, and means disposed in series with said source and said junction for resetting said junction from the finite voltage state to the zero voltage state.

Claim 18

A Josephson junction circuit comprising a current source, at least a single latching Josephson junction adapted for switching from a zero voltage state to a finite voltage state connected to said source, and means disposed in series with said source and said junction for resetting said junction from the finite voltage state to the zero voltage state.

Claim 19

A Josephson junction circuit as claimed in claim 13 wherein said resetting means comprises an impedance mismatch disposed in series with said junction.

Claim 20

A Josephson junction circuit comprising at least a single latching Josephson junction having a finite voltage state and a zero voltage state, means for switching said junction electrically connected thereto for switching said junction from the zero voltage state to the finite voltage state, the switching of said junction generating a current pulse transient, and means electrically connected to said junction for reflecting at least a portion of said current pulse transient said at least a portion being of sufficient magnitude to reset said junction from the finite voltage state to the zero voltage state.

Claim 21

A Josephson junction circuit comprising at least a single latching Josephson junction having a finite voltage state and a zero voltage state, means for switching said junction electrically connected thereto for switching said junction from the zero voltage state to the finite voltage state, the switching of said junction generating a current pulse transient, and means electrically connected to said junction for reflecting at least a portion of said current pulse transient said at least a portion being of sufficient magnitude to reset said junction from the finite voltage state to the zero voltage state.

Claim 22

A Josephson junction circuit as claimed in claim 15 wherein said means for reflecting comprises an impedance mismatch in series with said junction.

Claim 23

A Josephson junction circuit as claimed in claim 15 wherein said means for reflecting comprises a transmission line in series with said junction, said transmission line formed by a superconductor material overlying an insulator which overlies a ground plane conductor, said transmission line having at least two portions which have, respectively, different characteristic impedances, said two portions being in contact to form an impedance mismatch at the point of said contact.