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US4027381A Expired / Lapsed US ⏱️ 0.0 years remaining

Silicon gate ccd structure

Assignee: Texas Instruments Inc
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Filing: 1976-06-01
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Granted: 1977-06-07
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Expires: 1996-06-01
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Abstract

Abstract Processes for manufacturing two-phase charge coupled devices (CCDs) having marginally overlapping phase electrodes and utilizing a single insulating material. Offset self-alignment techniques are used to achieve accurate location of ion implanted potential well or potential barrier regions to achieve the required asymmetry of potential wells (or threshold voltages) in each gate region of the CCD with small bit or charge storage element sizes leading to structures having a high packing density. Fabrication of surface and buried channel structures is described.

Inventors

  • 👤 Al F. Tasch, Jr.
  • 👤 Robert C. Frye

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:51
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10D44/40; H10D44/45; H10D44/472; H10D44/474; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/335; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0198; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 216 words
In a method of fabricating a charge coupled device having adjacent overlapping phase electrodes separated from each other and from an underlying semiconductor substrate surface by a single insulator material, the steps of: forming spaced polycrystalline semiconductor strips on a layer of insulating material overlying said surface of the semiconductor substrate such that first and second portions of each polycrystalline semiconductor material strip are respectively separated from the said surface by relatively thin and thick areas of said insulating material, and exposed regions of said semiconductor surface occupy spaces between said strips; covering first portions of said exposed regions with masking material such that second portions of said exposed regions remain exposed, said second portions respectively defined by an edge of said masking material and an edge of a polycrystalline semiconductor strip; implanting dopant ions into said remaining exposed regions to modify the surface potential at said semiconductor surface in said remaining exposed regions; removing said masking material and forming a further layer of said insulating material over said exposed surface regions to the thickness of adjacent areas of insulating material beneath said polycrystalline semiconductor strips and to cover said polycrystalline semiconductor strips; and forming conductive electrodes over said further insulating material between said polycrystalline strips, said conductive electrodes having marginal portions overlapping adjacent polycrystalline strips.
Claim 2
Dependent Claim 216 words
In a method of fabricating a charge coupled device having adjacent overlapping phase electrodes separated from each other and from an underlying semiconductor substrate surface by a single insulator material, the steps of: forming spaced polycrystalline semiconductor strips on a layer of insulating material overlying said surface of the semiconductor substrate such that first and second portions of each polycrystalline semiconductor material strip are respectively separated from the said surface by relatively thin and thick areas of said insulating material, and exposed regions of said semiconductor surface occupy spaces between said strips; covering first portions of said exposed regions with masking material such that second portions of said exposed regions remain exposed, said second portions respectively defined by an edge of said masking material and an edge of a polycrystalline semiconductor strip; implanting dopant ions into said remaining exposed regions to modify the surface potential at said semiconductor surface in said remaining exposed regions; removing said masking material and forming a further layer of said insulating material over said exposed surface regions to the thickness of adjacent areas of insulating material beneath said polycrystalline semiconductor strips and to cover said polycrystalline semiconductor strips; and forming conductive electrodes over said further insulating material between said polycrystalline strips, said conductive electrodes having marginal portions overlapping adjacent polycrystalline strips.
Claim 3
Dependent Claim 27 words
A method according to claim 1, wherein said semiconductor substrate is a silicon substrate, said insulator material is silicon oxide, and said polycrystalline semiconductor material is silicon.
Claim 4
Dependent Claim 21 words
A method according to claim 1, wherein said dopant ions have opposite conductivity type from that of said semiconductor substrate surface.
Claim 5
Dependent Claim 18 words
A method according to claim 1, wherein said polycrystalline semiconductor strip electrodes extend from a common bus conductor.

References Cited (Backward Citations)

US3697786A Cited
US3967306A Cited
US3931674A Cited
US3924319A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-06-06 1980-12-06 1981-06-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-06-06 1984-12-06 1985-06-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-06-06 1988-12-06 1989-06-07 $7700.00 Window Closed / Lapsed

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