Patent US4023144A successfully refreshed from Google Patents.
US4023144A
Expired / Lapsed
US
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Parallel to serial digital converter
Assignee: United States Department of the Navy
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Filing: 1976-04-02
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Granted: 1977-05-10
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Expires: 1996-04-02
Abstract
Abstract A high speed parallel to serial digital converter includes a data shift rster, a control shift register and control circuitry. During a control cycle a control input comprising a set of control bits in parallel form is converted by the control shift register into serial form. The serialized control bits are coupled to a register load selector which responds to the control bits to appropriately signal the control circuitry so that at the end of the control cycle the converter will commence either another control cycle or a data cycle. During a data cycle an input data word comprising data bits in parallel form is converted by the data shift register into serial form. At the end of a data cycle timing circuitry signals the control circuitry to commence a reset cycle during which the converter is reset to commence another control cycle.
Inventors
- 👤 Harry J. Koenig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:10
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
280 words
An apparatus for accepting digital information in parallel form and transmitting digital information in serial form wherein said digital information comprises control information and data information, said apparatus comprising: a. a control input means for accepting said parallel-form control information; b. a control shift register means coupled to said control input means for converting said control information from parallel form to serial form during a control cycle of said apparatus; c. a data input means for accepting said parallel-form data information; d. a data shift register means coupled to said data input means for converting said data information from parallel form to serial form during a data cycle of said apparatus; e. control means coupled to said control shift register means and to said data shift register means for operating said apparatus in a control cycle or a data cycle and for preventing said apparatus from operating in both cycles at the same time; f. register selector means coupled to said control means and having its input coupled to the output of said control shift register means for responding to an instruction contained in the control information converted during a given control cycle to signal said control means to operate said apparatus in either another control cycle or a data cycle after the conclusion of the given control cycle; g. timing means coupled to said control means for regulating the time duration of each of said data cycles; h. a control coupling means for coupling the output of said control shift register means to the output of said apparatus; i. a data coupling means for coupling the output of said data shift register means to the output of said apparatus.
Claim 2
Independent Claim
280 words
An apparatus for accepting digital information in parallel form and transmitting digital information in serial form wherein said digital information comprises control information and data information, said apparatus comprising: a. a control input means for accepting said parallel-form control information; b. a control shift register means coupled to said control input means for converting said control information from parallel form to serial form during a control cycle of said apparatus; c. a data input means for accepting said parallel-form data information; d. a data shift register means coupled to said data input means for converting said data information from parallel form to serial form during a data cycle of said apparatus; e. control means coupled to said control shift register means and to said data shift register means for operating said apparatus in a control cycle or a data cycle and for preventing said apparatus from operating in both cycles at the same time; f. register selector means coupled to said control means and having its input coupled to the output of said control shift register means for responding to an instruction contained in the control information converted during a given control cycle to signal said control means to operate said apparatus in either another control cycle or a data cycle after the conclusion of the given control cycle; g. timing means coupled to said control means for regulating the time duration of each of said data cycles; h. a control coupling means for coupling the output of said control shift register means to the output of said apparatus; i. a data coupling means for coupling the output of said data shift register means to the output of said apparatus.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1 wherein each of said control cycles may be followed by a data cycle or by one or more control cycles.
Claim 4
Dependent Claim
29 words
The apparatus of claim 2 wherein the time duration of all of said control cycles is equal and the time duration of all of said data cycles is equal.
Claim 5
Dependent Claim
39 words
The apparatus of claim 3 wherein said control shift register means and said data shift register means each comprises a parallel to serial shift register means, each of said parallel to serial shift register means having a clock terminal.
Claim 6
Dependent Claim
51 words
The apparatus of claim 4 wherein a clock means is provided for simultaneously coupling clock pulses to the clock terminal of both the control shift register means and the data shift register means, each of said clock pulses being also coupled to said register selector means and to said timing means.
Claim 7
Dependent Claim
52 words
The apparatus of claim 5 wherein a control cycle commences when control information comprising a set of control bits in parallel form is loaded into said control shift register means, each of said sets of control bits including a start bit which has the same logic value in each control bit set.
Claim 8
Dependent Claim
30 words
The apparatus of claim 6 wherein a data cycle commences when data information comprising a set of data bits in parallel form is loaded into said data shift register means.
Claim 9
Dependent Claim
41 words
The apparatus of claim 7 wherein said register selector means responds to the start bit of the control information of a given control cycle to signal said control means to conclude the given control cycle and commence another cycle of operation.
Claim 10
Dependent Claim
75 words
The apparatus of claim 8 wherein said control coupling means and said data coupling means are coupled to the output of said apparatus through an output selector means for coupling only the output of the control shift register means to the output of said apparatus during each of said control cycles and for coupling only the output of the data shift register means to the output of said apparatus during each of said data cycles.
Claim 11
Dependent Claim
32 words
The apparatus of claim 9 wherein amplifying means are coupled between the output of said output selector means and the output of said apparatus for amplifying the digital output of said apparatus.
Claim 12
Dependent Claim
41 words
The apparatus of claim 10 wherein said apparatus accepts data information comprising parallel-form data words at a rate in excess of 125-kilowords per second and transmits data information comprising serial-form data words at a rate in excess of 10-megabits per second.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-09 | 1980-11-08 | 1981-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-09 | 1984-11-08 | 1985-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-09 | 1988-11-08 | 1989-05-10 | $7700.00 | Window Closed / Lapsed |