Serial-to-parallel and parallel-toserial buffer-converter using a core matrix

Claim 1

A DEVICE FOR DISTRIBUTING DATA UNITS TO CORRESPONDING OUTPUT LINES ON A SERIAL-BY-BIT BASIS COMPRISING: A MAGNETIC CORE MATRIX MEMORY IN WHICH SAID CORES ARE ARRANGED IN AN ARRAY OF ROWS AND COLUMNS; A SHIFT REGISTER; MEANS FOR APPLYING DATA UNITS IN PARALLEL TO SAID SHIFT REGISTER; MEANS FOR APPLYING THE CONTENTS OF SAID SHIFT REGISTER A BIT AT A TIME TO SAID MEMORY; CYCLIC MEANS FOR APPLYING SUCCEEDING OUTPUTS FROM SAID MEMORY TO SUCCEEDING ONES OF SAID OUTPUT LINES; BISTABLE MEANS FOR CONTROLLING THE MANNER IN WHICH CORES IN SAID MEMORY ARE TO BE ACCESSED, EACH ACCESS INCLUDING A READ-OUT CYCLE FOLLOWED BY A WRITE-IN CYCLE; MEANS RESPONSIVE TO SAID BISTABLE MEANS BEING IN ITS OF ITS TATES FOR CAUSING SAID CORES TO BE ACCESSED A ROW AT A TIME; MEANS RESPONSIVE TO SAID BISTABLE MEANS BEING IN ITS OTHER STATE FOR CAUSING SAID CORES TO BE ACCESSED A COLUMN AT A TIME; MEANS OPERABLE AFTER EACH ECCESS TO A CORE FOR SHIFTING SAID SHIFT REGISTER SO AS TO CAUSE A NEW BIT TO BE APPLIED TO SAID MEMORY AND FOR INCREMENTING SAID CYCLIC MEANS SO AS TO CAUSE A NEW BIT TO BE MEMORY TO A DIFFERENT ONE OF SAID OUTPUT LINES; MEANS RESPONSIVE TO THE ACCESSING OF A FULL ROW OR A FULL COLUMN OF SAID MEMORY FOR CAUSING SAID DATA UNIT APPLYING MEANS TO APPLY A NEW DATA UNIT TO SAID SHIFT REGISTER AND FOR INITIATING A NEW CYCLE OF SAID CYCLIC MEANS; AND MEANS RESPONSIVE TO ALL THE CORES IN SAID MEMORY BEING ACCESSED FOR ALTERING THE STATE OF SAID BISTABLE MEANS.

Claim 2

A DEVICE FOR DISTRIBUTING DATA UNITS TO CORRESPONDING OUTPUT LINES ON A SERIAL-BY-BIT BASIS COMPRISING: A MAGNETIC CORE MATRIX MEMORY IN WHICH SAID CORES ARE ARRANGED IN AN ARRAY OF ROWS AND COLUMNS; A SHIFT REGISTER; MEANS FOR APPLYING DATA UNITS IN PARALLEL TO SAID SHIFT REGISTER; MEANS FOR APPLYING THE CONTENTS OF SAID SHIFT REGISTER A BIT AT A TIME TO SAID MEMORY; CYCLIC MEANS FOR APPLYING SUCCEEDING OUTPUTS FROM SAID MEMORY TO SUCCEEDING ONES OF SAID OUTPUT LINES; BISTABLE MEANS FOR CONTROLLING THE MANNER IN WHICH CORES IN SAID MEMORY ARE TO BE ACCESSED, EACH ACCESS INCLUDING A READ-OUT CYCLE FOLLOWED BY A WRITE-IN CYCLE; MEANS RESPONSIVE TO SAID BISTABLE MEANS BEING IN ITS OF ITS TATES FOR CAUSING SAID CORES TO BE ACCESSED A ROW AT A TIME; MEANS RESPONSIVE TO SAID BISTABLE MEANS BEING IN ITS OTHER STATE FOR CAUSING SAID CORES TO BE ACCESSED A COLUMN AT A TIME; MEANS OPERABLE AFTER EACH ECCESS TO A CORE FOR SHIFTING SAID SHIFT REGISTER SO AS TO CAUSE A NEW BIT TO BE APPLIED TO SAID MEMORY AND FOR INCREMENTING SAID CYCLIC MEANS SO AS TO CAUSE A NEW BIT TO BE MEMORY TO A DIFFERENT ONE OF SAID OUTPUT LINES; MEANS RESPONSIVE TO THE ACCESSING OF A FULL ROW OR A FULL COLUMN OF SAID MEMORY FOR CAUSING SAID DATA UNIT APPLYING MEANS TO APPLY A NEW DATA UNIT TO SAID SHIFT REGISTER AND FOR INITIATING A NEW CYCLE OF SAID CYCLIC MEANS; AND MEANS RESPONSIVE TO ALL THE CORES IN SAID MEMORY BEING ACCESSED FOR ALTERING THE STATE OF SAID BISTABLE MEANS.