Sequence control system with timed operations

Claim 2

A logic circuit for determining the completion within an allotted time of one of a series of sequential operations comprising means for responding to a signal indicating the start of said allotted time and to a series of timing signals thereafter by providing an output signal indicative of the passage of said allotted time for completion of an operation, bistable latch means for receiving and storing a signal indicating the completion of said operation, and gate means coupled to said latch means and to said timing signal responsive means for providing a signal indicating the sequence of occurrence of said operation completion signal and said allotted time passage signal.

Claim 3

A logic circuit as claimed in claim 1 wherein said timing signal responsive means includes a digital counter for counting a predetermined number of said timing signals.

Claim 4

A logic circuit as claimed in claim 1 further comprising switch means between said latch means and said gate means for programming the time occurrence of a signal from said gate means indicating completion of said operation within the allotted time.

Claim 5

A logic circuit as claimed in claim 1 further comprising means between said gate means and said timing signal responsive means for programming the time occurence of a signal from said gate means indicating passage of the allotted time prior to reception of said operation completion signal.

Claim 6

A logic circuit as claimed in claim 4 wherein said means for programming the time occurrence of a signal from said gate means indicating passage of the allotted time prior to reception of said operation completion signal includes a digital counter connected to the output of said timing signal responsive means for delaying the occurrence of said signal indicating the passage of the allotted time prior to reception of said operation completion signal.

Claim 7

A control system for checking and controlling a sequence of operations comprising timing means for providing timing signals at intervals establishing a predetermined allotted time for completion of each operation, and a plurality of logic circuits corresponding to the number of operations to be performed, each logic circuit comprising: means responsive to said timing signals for providing an output signal indicative of the passage of said allotted time for completion of an operation, bistable latch means for receiving and storing a signal indicating the completion of an operation, and gate means coupled to said latch means and to said timing signal responsive means for providing a signal to initiate the next sequential operation when said operation completion signal occurs prior to said allotted time passage signal and for providing a signal to discontinue the sequence of operations if said allotted time passage signal occurs prior to said operation completion signal, said gate means being coupled to the next sequential logic circuit and to a preceding logic circuit for enabling said next circuit to respond to said timing signals and for resetting said preceding logic circuit when said operation completion signal occurs prior to said allotted time passage signal.

Claim 8

A control system for checking and controlling a sequence of operations comprising timing means for providing timing signals at intervals establishing a predetermined allotted time for completion of each operation, and a plurality of logic circuits corresponding to the number of operations to be performed, each logic circuit comprising: means responsive to said timing signals for providing an output signal indicative of the passage of said allotted time for completion of an operation, bistable latch means for receiving and storing a signal indicating the completion of an operation, and gate means coupled to said latch means and to said timing signal responsive means for providing a signal to initiate the next sequential operation when said operation completion signal occurs prior to said allotted time passage signal and for providing a signal to discontinue the sequence of operations if said allotted time passage signal occurs prior to said operation completion signal, said gate means being coupled to the next sequential logic circuit and to a preceding logic circuit for enabling said next circuit to respond to said timing signals and for resetting said preceding logic circuit when said operation completion signal occurs prior to said allotted time passage signal.

Claim 9

A control system as claimed in claim 6 wherein each of said timing signal responsive means is a digital counter for counting a predetermined number of said timing signals.

Claim 10

A control system for checking and controlling a sequence of operations comprising timing means for providing timing signals at intervals establishing a predetermined allotted time for completion of each operation, and a plurality of logic circuit corresponding to the number of operations to be performed, each logic circuit comprising: a digital counter for counting said timing pulses and for providing an output signal at a predetermined count, a bistable latch circuit for receiving and storing a signal indicating the completion of an operation, a first gate having an input coupled to an output of said latch circuit and another input coupled to an output of said counter for providing an output signal indicating the completion of an operation prior to the passage of an allotted time, and a second gate having an input coupled to another output of said latch circuit and another input coupled to the output of said counter for providing a signal indicating the passage of the allotted time prior to the completion of the operation, the output of said first gate being coupled to an input of the counter of the next sequential logic circuit for permitting the counter to count only if said output signal is provided from said first gate, the output of said first gate also being coupled to reset a sequentially preceding latch means.

Claim 11

A control system for checking and controlling a sequence of operations comprising timing means for providing timing signals at intervals establishing a predetermined allotted time for completion of each operation, and a plurality of logic circuit corresponding to the number of operations to be performed, each logic circuit comprising: a digital counter for counting said timing pulses and for providing an output signal at a predetermined count, a bistable latch circuit for receiving and storing a signal indicating the completion of an operation, a first gate having an input coupled to an output of said latch circuit and another input coupled to an output of said counter for providing an output signal indicating the completion of an operation prior to the passage of an allotted time, and a second gate having an input coupled to another output of said latch circuit and another input coupled to the output of said counter for providing a signal indicating the passage of the allotted time prior to the completion of the operation, the output of said first gate being coupled to an input of the counter of the next sequential logic circuit for permitting the counter to count only if said output signal is provided from said first gate, the output of said first gate also being coupled to reset a sequentially preceding latch means.

Claim 12

A control system as claimed in claim 8 further comprising switch means between said latch circuit and said first gate for programming the time occurrence of said signal indicating the completion of an operation within the allotted time.

Claim 13

A control system as claimed in claim 8 further comprising an additional counter connected to the output of said digital counter for delaying the occurrence of a signal indicating the passage of the allotted time prior to the completion of the operation.