Dynamic shift register cell

Claim 2

An integrated circuit dynamic shift register stage having an input and output terminal comprising, in combination: first, second and third terminals to which respective control voltages may be applied; first and second charge storage means coupled between a first node and a point at a reference potential and a second node and said point at said reference potential, respectively, said second node comprising said output terminal; a first metal-oxide-semiconductor (MOS) transistor of a first conductivity type having a conduction path and a control electrode, said conduction path connected between said first node and said first terminal and said control electrode comprising said input terminal; a second MOS transistor of a second conductivity type having a conduction path and a control electrode, said second transistor conduction path connected in parallel connection with said first transistor conduction path and said second transistor control electrode connected to said second terminal; a third MOS transistor of said second conductivity type having a conduction path and a control electrode, said third transistor conduction path connected between said second node and said first terminal and said third transistor control electrode connected to said first node; and a fourth MOS transistor of said first conductivity type having a conduction path and a control electrode, said fourth transistor conduction path connected in parallel connection with said third transistor conduction path and said fourth transistor control electrode connected to said third terminal.

Claim 3

A shift register cell comprising, in combination; first, second, third and fourth transistors, said first and fourth transistors being of a first conductivity type and said second and third transistors being of a second conductivity type, each having a conduction path and a control electrode for controlling the conductivity of said path; first and second capacitances; means responsive to a control voltage applied to the control electrode of said first transistor for precharging said first capacitance to a reference voltage level through the conduction path of said first transistor; means responsive to a signal applied to the control electrode of said second transistor for changing the level of charge stored in said first capacitance, via the conduction path of said second transistor, when the signal lever is such that the second transistor turns on and for retaining the charge stored in said first capacitance at its reference level when the signal level is such that said second transistor remains off; means responsive to a control signal applied to the control electrode of said third transistor for precharging said second capacitance to a reference voltage level through the conduction path of said third transistor; and the control electrode of said fourth transistor being coupled to said first capacitance and responsive to the voltage thereat for changing the level of the charge stored in said second capacitance via the conduction path of said fourth transistor, when the charge stored in said first capacitance is at one level, and for maintaining said fourth transistor cut off when the charge stored in said first capacitance is at a second level, thereby retaining the charge stored in said second capacitance at its reference level.

Claim 4

A shift register cell comprising, in combination; first, second, third and fourth transistors, said first and fourth transistors being of a first conductivity type and said second and third transistors being of a second conductivity type, each having a conduction path and a control electrode for controlling the conductivity of said path; first and second capacitances; means responsive to a control voltage applied to the control electrode of said first transistor for precharging said first capacitance to a reference voltage level through the conduction path of said first transistor; means responsive to a signal applied to the control electrode of said second transistor for changing the level of charge stored in said first capacitance, via the conduction path of said second transistor, when the signal lever is such that the second transistor turns on and for retaining the charge stored in said first capacitance at its reference level when the signal level is such that said second transistor remains off; means responsive to a control signal applied to the control electrode of said third transistor for precharging said second capacitance to a reference voltage level through the conduction path of said third transistor; and the control electrode of said fourth transistor being coupled to said first capacitance and responsive to the voltage thereat for changing the level of the charge stored in said second capacitance via the conduction path of said fourth transistor, when the charge stored in said first capacitance is at one level, and for maintaining said fourth transistor cut off when the charge stored in said first capacitance is at a second level, thereby retaining the charge stored in said second capacitance at its reference level.

Claim 5

The combination recited in claim 2 wherein said means for precharging said first capacitance comprises a terminal coupled through said first transistor conduction path to one terminal of said capacitance, said terminal at a potential representing a first binary value.

Claim 6

The combination recited in claim 3 wherein the means for precharging said second capacitance comprises a terminal coupled through said third transistor conduction path to one terminal of said second capacitance, said terminal at a potential representing a second binary value.

Claim 7

The combination recited in claim 2 wherein said first and fourth transistors comprise metal-oxide-semiconductor (MOS) transistors of a first conductivity type and said second and third transistors comprise MOS transistors of a second conductivity type.

Claim 8

The combination recited in claim 5 wherein the conduction path impedances of said first and third transistors is large compared with the conduction path impedances of said fourth and second transistors, respectively.

Claim 9

A dynamic shift register stage comprising: first, second and third terminals; four switches, said switches being the sole switches in said stage, each switch including a conduction path and control means for controlling the impedance of said conduction path, the conduction paths of the first and second of said switches connected between said first and second terminals, the conduction paths of the third and fourth of said switches connected between said first and third terminals; two capacitances, one connected between said second terminal and a point of reference potential and the other between said third terminal and said point of reference potential; a direct connection between said second terminal and the control means of said fourth transistor; an input terminal for said stage at the control means of said second switch; an output terminal for said stage at said third terminal; means coupled to the control means of said first and third switches for concurrently closing said first switch and opening said third switch and for concurrently closing said third switch and opening said first switch; and means coupled to said first terminal for applying a signal thereto having first and second voltage levels, said signal assuming said first level during the interval when said first switch is closed and said second level during the interval when said first switch is open.

Claim 10

A dynamic shift register stage comprising: first, second and third terminals; four switches, said switches being the sole switches in said stage, each switch including a conduction path and control means for controlling the impedance of said conduction path, the conduction paths of the first and second of said switches connected between said first and second terminals, the conduction paths of the third and fourth of said switches connected between said first and third terminals; two capacitances, one connected between said second terminal and a point of reference potential and the other between said third terminal and said point of reference potential; a direct connection between said second terminal and the control means of said fourth transistor; an input terminal for said stage at the control means of said second switch; an output terminal for said stage at said third terminal; means coupled to the control means of said first and third switches for concurrently closing said first switch and opening said third switch and for concurrently closing said third switch and opening said first switch; and means coupled to said first terminal for applying a signal thereto having first and second voltage levels, said signal assuming said first level during the interval when said first switch is closed and said second level during the interval when said first switch is open.

Claim 11

The combination as set forth in claim 7 wherein said means coupled to the control means of said first and third switches comprises first and second signal sources coupled to the control means of said first and third switches, respectively.

Claim 12

The combination as set forth in claim 7 further including a direct current connection between the control means of said first and third switches.

Claim 13

The combination as set forth in claim 9 wherein said means coupled to the control means of said first and third switches comprises a signal source connected to said direct current connection.

Claim 14

The combination as set forth in claim 7 wherein said four switches comprise first, second, third and fourth metal-oxide-semiconductor transistor respectively, each transistor having a conduction path and a control electrode, said control electrode comprising said control means.

Claim 15

The combination as set forth in claim 11 wherein said first and fourth transistors are of a first conductivity type and said second and third transistors are of a second conductivity type.