Booster circuits

Claim 2

In a voltage-boosting circuit, in combinations: input means for supplying a voltage wave alternating between a first and a second level; a field-effect transistor provided with a semi-conductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction with a predetermined threshold voltage, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; circuit means connecting said source electrode to a point of fixed reference potential; a first lead extending from said input means to said drain electrode for delivering said voltage wave thereto; a series capacitor in said first lead; and a second lead extending from said input means to said gate for delivering said voltage wave thereto in inverted relationship with the voltage wave supplied to said drain electrode through said series capacitor, the relative polarities of the voltages at said drain electrode and said gate reversing during successive alternations of said voltage wave whereby said transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of said drain and source electrodes.

Claim 3

The combination defined in claim 1 wherein said circuit means comprises a conductor carrying a constant voltage.

Claim 4

The combination defined in claim 1 wherein said circuit means comprises a condenser inserted between said source electrode and said point of fixed reference potential.

Claim 5

The combination defined in claim 3, further comprising a shunt diode inserted between said drain electrode and said point of fixed reference potential with a polarity opposite that of said P/N junction.

Claim 6

The combination defined in claim 4 wherein said shunt diode comprises a second field-effect transistor complementary to the first-mentioned transistor connected in parallel therewith.

Claim 7

The combination defined in claim 1 wherein said circuit means comprises an ancillary booster stage including a condenser in series with said second lead and a shunt diode connected between said gate and said source electrode in series-opposed relationship with said P/N junction.

Claim 8

In an electronic clockwork, in combination: input means for supplying a square-wave voltage; a field-effect transistor provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction with a predetermined threshold voltage, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; circuit means connecting said source electrode to a point of fixed reference potential; a first lead extending from said input means to said drain electrode for delivering said square-wave voltage thereto; a series capacitor in said first lead; and a second lead extending from said input means to said gate for delivering said square-wave voltage thereto in inverted relationship with the square-wave voltage supplied to said drain electrode through said series capacitor, the relative polarities of the voltages at said drain electrode and said gate reversing during successive alternations of said square-wave voltage whereby said transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of said drain and source electrodes.

Claim 9

In an electronic clockwork, in combination: input means for supplying a square-wave voltage; a field-effect transistor provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction with a predetermined threshold voltage, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; circuit means connecting said source electrode to a point of fixed reference potential; a first lead extending from said input means to said drain electrode for delivering said square-wave voltage thereto; a series capacitor in said first lead; and a second lead extending from said input means to said gate for delivering said square-wave voltage thereto in inverted relationship with the square-wave voltage supplied to said drain electrode through said series capacitor, the relative polarities of the voltages at said drain electrode and said gate reversing during successive alternations of said square-wave voltage whereby said transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of said drain and source electrodes.

Claim 10

The combination defined in claim 7 wherein said circuit means comprises a condenser inserted between said source electrode and said point of fixed reference potential.

Claim 11

In a voltage-boosting circuit, in combination: input means for supplying a voltage wave alternating between a first and a second level;

Claim 12

In a voltage-boosting circuit, in combination: input means for supplying a voltage wave alternating between a first and a second level;

Claim 13

a pair of complementary field-effect transistors each provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; first circuit means connecting the source electrode of each transistor to a point of fixed reference potential; capacitive second circuit means connecting said input means to the drain electrodes of both transistors for delivering said voltage wave thereto; third circuit means connecting said input means to the gates of both transistors for delivering said voltage wave thereto in inverted relationship with the voltage wave supplied to said drain electrodes by said second circuit means, the relative polarities of the voltages at the drain electrode and the gate of each transistor reversing during successive alternations of said voltage wave whereby each transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of the drain and source electrodes thereof; and joint output means for said transistors producing a magnified replica of said voltage wave.

Claim 14

a pair of complementary field-effect transistors each provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; first circuit means connecting the source electrode of each transistor to a point of fixed reference potential; capacitive second circuit means connecting said input means to the drain electrodes of both transistors for delivering said voltage wave thereto; third circuit means connecting said input means to the gates of both transistors for delivering said voltage wave thereto in inverted relationship with the voltage wave supplied to said drain electrodes by said second circuit means, the relative polarities of the voltages at the drain electrode and the gate of each transistor reversing during successive alternations of said voltage wave whereby each transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of the drain and source electrodes thereof; and joint output means for said transistors producing a magnified replica of said voltage wave.

Claim 15

The combination defined in claim 9 wherein said circuit means comprises a condenser inserted between said source electrode and said point of fixed reference potential.

Claim 16

The combination defined in claim 9 wherein said output means includes a Cockcroft circuit with input terminals respectively connected to said drain electrodes.

Claim 17

In an electronic clockwork, in combination: input means for supplying a square-wave voltage; a pair of complementary field-effect transistors each provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; first circuit means connecting the source electrode of each transistor to a point of fixed reference potential; capacitive second circuit means connecting said input means to the drain electrodes of both transistors for delivering said square-wave voltage thereto; third circuit means connecting said input means to the gates of both transistors for delivering said square-wave voltage thereto in inverted relationship with the square-wave voltage supplied to said drain electrodes by said second circuit means, the relative polarities of the square-wave voltages at the drain electrode and the gate of each transistor reversing during successive alternations of said square-wave voltage whereby each transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of the drain and source electrodes thereof; and joint output means for said transistors producing a magnified replica of said square-wave voltage.

Claim 18

In an electronic clockwork, in combination: input means for supplying a square-wave voltage; a pair of complementary field-effect transistors each provided with a semiconductive substrate, a source electrode connected directly to said substrate, a drain electrode coupled to said substrate through a P/N junction, said drain and source electrodes being located at opposite ends of a channel region of said substrate, and a gate controlling the conductivity of said channel region; first circuit means connecting the source electrode of each transistor to a point of fixed reference potential; capacitive second circuit means connecting said input means to the drain electrodes of both transistors for delivering said square-wave voltage thereto; third circuit means connecting said input means to the gates of both transistors for delivering said square-wave voltage thereto in inverted relationship with the square-wave voltage supplied to said drain electrodes by said second circuit means, the relative polarities of the square-wave voltages at the drain electrode and the gate of each transistor reversing during successive alternations of said square-wave voltage whereby each transistor is cut off during every other alternation and conducts in the intervening alternations with resulting equalization of the voltages of the drain and source electrodes thereof; and joint output means for said transistors producing a magnified replica of said square-wave voltage.

Claim 19

The combination defined in claim 12 wherein said circuit means comprises a condenser inserted between said source electrode and said point of fixed reference potential.

Claim 20

In a voltage-boosting circuit, in combination: a chain of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of said diodes; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of said diodes; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and an output capacitor connected between the last diode of said chain and a point of fixed reference potential, said last diode and said capacitor having a common load terminal whose potential relative to said reference potential varies with an amplitude substantially exceeding those of said square waves.

Claim 21

In a voltage-boosting circuit, in combination: a chain of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of said diodes; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of said diodes; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and an output capacitor connected between the last diode of said chain and a point of fixed reference potential, said last diode and said capacitor having a common load terminal whose potential relative to said reference potential varies with an amplitude substantially exceeding those of said square waves.

Claim 22

The combination defined in claim 14 wherein said supply means comprises a pair of complementary field-effect transistors.

Claim 23

In a voltage-boosting circuit, in combination: two relatively inverted chains of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of each of said chains; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of each of said chains; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and a pair of output capacitors respectively connected between the last diode of each chain and a point of fixed potential, said last diodes respectively defining with said capacitors a pair of load terminals whose relative potential varies with an amplitude substantially exceeding those of said square waves.

Claim 24

In a voltage-boosting circuit, in combination: two relatively inverted chains of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of each of said chains; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of each of said chains; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and a pair of output capacitors respectively connected between the last diode of each chain and a point of fixed potential, said last diodes respectively defining with said capacitors a pair of load terminals whose relative potential varies with an amplitude substantially exceeding those of said square waves.

Claim 25

In an electronic clockwork, in combination: a chain of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of said diodes; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of said diodes; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and an output capacitor connected between the last diode of said chain and a point of fixed reference potential, said last diode and said capacitor having a common load terminal whose potential relative to said reference potential varies with an amplitude substantially exceeding those of said square waves.

Claim 26

In an electronic clockwork, in combination: a chain of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of said diodes; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of said diodes; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and an output capacitor connected between the last diode of said chain and a point of fixed reference potential, said last diode and said capacitor having a common load terminal whose potential relative to said reference potential varies with an amplitude substantially exceeding those of said square waves.

Claim 27

The combination defined in claim 17 wherein said supply means comprises a pair of complementary field-effect transistors.

Claim 28

In an electronic clockwork, in combination: two relatively inverted chains of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of each of said chains; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of each of said chains; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and a pair of output capacitors respectively connected between the last diode of each chain and a point of fixed potential, said last diodes respectively defining with said capacitors a pair of load terminals whose relative potential varies with an amplitude substantially exceeding those of said square waves.

Claim 29

In an electronic clockwork, in combination: two relatively inverted chains of serially interconnected diodes forming junctions therebetween; a first circuit branch with a first input and with a series of first capacitive networks connected between said first input and odd-numbered junctions of each of said chains; a second circuit branch with a second input and with a series of second capacitive networks connected between said second input and even-numbered junctions of each of said chains; semiconductive supply means for respectively applying two mutually dephased square waves to said inputs; and a pair of output capacitors respectively connected between the last diode of each chain and a point of fixed potential, said last diodes respectively defining with said capacitors a pair of load terminals whose relative potential varies with an amplitude substantially exceeding those of said square waves.