Semiconductor integrated circuit transistor detector array for channel electron multiplier

Claim 1

Semiconductor apparatus which comprises a. a semiconductor wafer of essentially one type relatively low electrical conductivity including an array of essentially mutually parallel relatively high conductivity elongated common bus strip regions of opposite type conductivity in said wafer, each of said bus regions being bounded on one side by a major surface of the semiconductor wafer; b. an insulating layer coating said major surface of the semiconductor wafer; c. an array of metal plates located on an exposed surface of the insulating layer for collecting electrons incident on said plates; d. electrically conductive means for connecting each metal plate through a different aperture in the insulating layer to a different localized surface zone in a first array of localized surface zones in said wafer, said localized zones of opposite type conductivity to said one type in said wafer, each said zone being isolated from all the strip regions; e. a second array of localized surface zones of said opposite type conductivity in said wafer, each said zone in the second array being isolated from all the strip regions and from all the zones in the first array, each zone in the second array located proximate to a corresponding zone in the first array, each zone of the second array being connected to an output bus electrode through a different aperture in the insulating layer; and f. dual electrode gating means located in said insulating layer for controlling the surface conductivity of the semiconductor wafer between each localized zone of the first array and its said corresponding proximate localized zone in the second array, one of said electrode means being connected to one of the common bus regions through an aperture in the insulating layer and the other of said electrode means being elongated to form a common bus electrode essentially orthogonal to the common bus regions.