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US4015140A
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Multiplier for producing phase shift error-free signal representing product of out-of-phase inputs
Assignee: General Electric Co
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Filing: 1975-12-05
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Granted: 1977-03-29
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Expires: 1995-12-05
Abstract
Abstract Metering kWh in an electrical system is accomplished by generating pairs of analog signals, representing current and voltage variables. Each pair of analog signals is multiplied together in a direct pulse-width conversion in a time-division multiplier network. A constant amplitude triangular generator is associated with the multiplier and the multiplier is implemented using C-MOS technology. A separate direct pulse-width multiplier network is provided for multiplying without introducing any phase shift each of the pairs of analog signals to form a series of width and amplitude-modulated pulse signals. The series of modulated pulse signals is converted in, for example, a low-pass filter to a signal having an amplitude representative of average power. For polyphase systems, the signals delivered from each of the multiplier channels are summed at the low-pass filter. An analog-to-pulse rate converter is used for converting the signal representing average power to another series of output pulse signals having a variable signal repetition rate proportional to average power, each output pulse signal representing a quantized amount of electrical energy. A stepping switch and register perform conventional accumulation, storage and display functions in response to the series of output pulse signals delivered thereto.
Inventors
- 👤 Miran Milkovic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:33
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/066; G; G01; G01R; G01R21/00; G01R21/127; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/161
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A multiplier for producing an output signal free of phase shift error and representative of the product of two out-of-phase input analog signals comprising means for generating a cyclically varying reference signal, comparator means for linearly superimposing said reference signal and one of said analog signals to form a pulse train width-modulated in accordance with the comparison of said reference signal with the one analog signal, a selectively actuated bipolar switch directly coupling the other analog signal that is out-of-phase with said one analog signal to the multiplier output, said switch being actuated by the width-modulated pulse train to form at the multiplier output an output pulse train which is width-modulated in accordance with the one analog signal and amplitude-modulated in accordance with the other analog signal.
Claim 2
Dependent Claim
127 words
A multiplier for producing an output signal free of phase shift error and representative of the product of two out-of-phase input analog signals comprising means for generating a cyclically varying reference signal, comparator means for linearly superimposing said reference signal and one of said analog signals to form a pulse train width-modulated in accordance with the comparison of said reference signal with the one analog signal, a selectively actuated bipolar switch directly coupling the other analog signal that is out-of-phase with said one analog signal to the multiplier output, said switch being actuated by the width-modulated pulse train to form at the multiplier output an output pulse train which is width-modulated in accordance with the one analog signal and amplitude-modulated in accordance with the other analog signal.
Claim 3
Dependent Claim
112 words
Apparatus in accordance with claim 1 wherein said multiplier includes means for generating an additional analog signal which is equal in amplitude to said other analog signal but phase-shifted 180° with respect thereto, and wherein said bipolar switch comprises an output terminal and first and second input terminals, respective first and second switching elements coupling first and second input terminals to said output terminal, means coupling said other analog signal to said first input terminal and said additional analog signal to said second input terminal, said first and second switching elements having switching control inputs, and means coupling said width-modulated pulse train to said switching control inputs for controlling switching of same.
Claim 4
Dependent Claim
75 words
Apparatus in accordance with claim 2 wherein each of said first and second switching elements comprises a complementary pair of MOS field effect transistors and including coupling means for coupling said width-modulated pulse train to one of the MOS field effect transistors in each pair, and additional coupling means for phase-shifting said width-modulated pulse train by 180° and coupling said phase-shifted width-modulated pulse train to the other MOS field effect transistor in each complementary pair.
Claim 5
Dependent Claim
122 words
Apparatus in accordance with claim 1 wherein said bipolar switch comprises first and second input terminals, means coupling the other analog signal across the first and second input terminals, an output terminal and a reference potential terminal, a first switching element coupling said first input terminal to said output terminal, a second switching element coupling said reference potential terminal to said first input terminal, a third switching element coupling said second input terminal to said reference potential terminal, and a fourth switching element coupling said second input terminal to said output terminal, each of said first, second, third and fourth switching elements having control inputs, and means coupling said width-modulated pulse train to said switching control inputs for controlling switching of same.
Claim 6
Dependent Claim
73 words
Apparatus in accordance with claim 4 wherein each of said first, second, third and fourth switching elements comprises a complementary pair of MOS field effect transistors and including first means coupling said width-modulated pulse train to one of the MOS field effect transistors in each pair and second means for phase shifting the width-modulated pulse train by 180° and coupling said phase shifted pulse train to the other transistor in each complementary pair.
Claim 7
Dependent Claim
68 words
Apparatus in accordance with claim 1 wherein said means for generating a cyclically varying reference signal comprises an integrator having an input and an output, first and second reference potential sources of equal amplitude and opposite polarity, and switching means for alternately and cyclically coupling said first and second reference potential sources to said integrator input whereby the cyclically varying reference signal is generated at the integrator output.
Claim 8
Dependent Claim
35 words
Apparatus in accordance with claim 1 wherein said reference potential sources are of constant amplitude so that the output of the integrator comprises an alternating increasing and decreasing ramp signal forming a triangular reference wave.
Claim 9
Dependent Claim
190 words
Apparatus in accordance with claim 7 wherein said switching means comprises first and second comparators, said first comparator having said first reference potential coupled to one of its inputs and said second comparator having said second reference potential coupled to one of its inputs, each of said first and second comparators having said integrator outputs coupled to the other of its inputs, logic means interconnecting the outputs of said first and second comparators, said logic means having first and second output switching means having first and second input terminals and an output terminal, means coupling said first and second input terminals to said first and second reference potential sources, respectively, means coupling said switching means output terminal to said integrator input terminal, a first switch element having a control input and coupling said switching means first input terminal to said switching means output terminal, a second switch element having a control input and coupling said switching means second input terminal to said switching means output terminal, and means coupling said first and second outputs of said logic means to said control inputs of said first and second switch elements, respectively.
Claim 10
Dependent Claim
24 words
Apparatus in accordance with claim 8 wherein each of said first and second switch elements comprises a complementary pair of MOS field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-28 | 1980-09-27 | 1981-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-28 | 1984-09-27 | 1985-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-28 | 1988-09-27 | 1989-03-29 | $7700.00 | Window Closed / Lapsed |