US3562553A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplier circuit
Assignee: Individual
•
Filing: 1968-10-21
•
Granted: 1971-02-09
•
Expires: 1988-10-21
Abstract
Abstract A multiplier including field effect transistor (FET) devices wherein an FET correction means is employed to substantially minimize nonlinearity and error in multiplier operation.
Inventors
- 👤 Allen R Roth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:34
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
100 words
A multiplier comprising: a field effect transistor multiplier means for receiving two input signals and for generating an output signal representative of the products of said input signals, said output signal containing a nonlinearity; a field effect transistor correction means for receiving only one of said input signals and providing an error correction output signal having a magnitude that tends to reduce said error signal; and means for combining the output signal from said multiplier means and said correction means to reduce said nonlinearity whereby an output product signal is provided with the nonlinearity reduced by an order of magnitude.
Claim 2
Dependent Claim
100 words
A multiplier comprising: a field effect transistor multiplier means for receiving two input signals and for generating an output signal representative of the products of said input signals, said output signal containing a nonlinearity; a field effect transistor correction means for receiving only one of said input signals and providing an error correction output signal having a magnitude that tends to reduce said error signal; and means for combining the output signal from said multiplier means and said correction means to reduce said nonlinearity whereby an output product signal is provided with the nonlinearity reduced by an order of magnitude.
Claim 3
Dependent Claim
18 words
The multiplier defined in claim 1 wherein said correcTion means includes a plurality of field effect transistor devices.
Claim 4
Dependent Claim
18 words
The multiplier defined in claim 2 wherein said multiplier means includes a plurality of field effect transistor devices.
Claim 5
Dependent Claim
41 words
The multiplier defined in claim 3 wherein said one input signal coupled to those said correction means and said multiplier means is coupled to the same electrode of a field effect transistor device in said multiplier means and said correction means.
Claim 6
Dependent Claim
117 words
The multiplier defined in claim 1 wherein said multiplier means comprises: a first field effect transistor and a second field effect transistor; said correction means comprises a third field effect transistor and a fourth field effect transistor; said field effect transistors each having first, second and third electrodes, said first electrode in said field effect transistors coupled to input signals having not necessarily substantially equal magnitudes; said second electrodes in said field effect transistors of the multiplier means coupled to input signal having substantially equal magnitudes; said second electrodes in said field effect transistors in the correction means coupled to substantially equal potentials; said third electrodes in said field effect transistors coupled to the means for combining.
References Cited (Backward Citations)
US3368066A
Cited
US3487164A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-08 | 1974-08-10 | 1975-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-08 | 1978-08-10 | 1979-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-08 | 1982-08-10 | 1983-02-09 | $7700.00 | Window Closed / Lapsed |