Circuit arrangement for placing information in a programmable ecl read only memory

Claim 1

In a programmable read-only memory of the type having a matrix of intersecting column and row lines with a respective storage cell at and connecting the lines at the individual intersections, each storage cell having a circuit element connected to one of the lines and a current interruptable resistor connecting the circuit element to the other of the lines, column selection means for selecting column lines, and row switches connected to the row lines for selecting rows in response to address signals, each row switch comprising a differential amplifier having parallel connected control transistors controlled by the address signals and a reference transistor, and an emitter follower connecting the collectors of the control transistors to the respective row line, the improvement therein comprising: an input for connection to a switched voltage source to receive a first voltage during a reading operation and a second voltage during an information input operation; and switch means for each row switch including a current path connected between said input and the associated row line and a control input connected to the reference transistor of the differential amplifier, said switch means operated by said row switch upon selection of the associated row line and ineffective with respect to the row line when said input receives the first voltage and effective when said input receives the second voltage to support a current flow which is necessary for interrupting the storage cell resistors assigned to the associated row line and to selected column lines.