US4004140A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital attenuator
Assignee: NTT Inc
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Filing: 1974-09-20
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Granted: 1977-01-18
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Expires: 1994-09-20
Abstract
Abstract A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of Pout = alpha Pin + N where Pout = output PCM signal Pin = input PCM signal processed by a compressor alpha = A REAL NUMBER SATISFYING THE CONDITION 0 < alpha < 1, AND N = a real number larger than or equal to 0.
Inventors
- 👤 Kazuto Izumi
- 👤 Kazuo Izumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:58
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/002; H03H; H03H17/00; H03H17/0054
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
114 words
A digital attenuator comprising input terminal means for receiving an input PCM signal, a pattern shift circuit connected to said input terminal means for shifting signals applied thereto to the lower digit side, a specific pattern generating circuit for generating an integer pattern, an adder connected to add said integer pattern to the output of said pattern shift circuit, a comparator connected to compare the output signal of said adder with signals applied to said input terminal means, an output terminal, and a switching circuit responsive to said comparator and connected to apply the lower of the signals at said input terminal means and at the output of said adder to said output terminal.
Claim 2
Dependent Claim
114 words
A digital attenuator comprising input terminal means for receiving an input PCM signal, a pattern shift circuit connected to said input terminal means for shifting signals applied thereto to the lower digit side, a specific pattern generating circuit for generating an integer pattern, an adder connected to add said integer pattern to the output of said pattern shift circuit, a comparator connected to compare the output signal of said adder with signals applied to said input terminal means, an output terminal, and a switching circuit responsive to said comparator and connected to apply the lower of the signals at said input terminal means and at the output of said adder to said output terminal.
Claim 3
Independent Claim
56 words
The method of attenuating a PCM signal comprising shifting said PCM signal to the lower digit side to produce a shifted signal, generating an integer pattern, adding said integer pattern to said shifted signal, and selecting the lower of said PCM signal and the result of third step of adding to produce an output PCM signal.
Claim 4
Independent Claim
56 words
The method of attenuating a PCM signal comprising shifting said PCM signal to the lower digit side to produce a shifted signal, generating an integer pattern, adding said integer pattern to said shifted signal, and selecting the lower of said PCM signal and the result of third step of adding to produce an output PCM signal.
Claim 5
Independent Claim
159 words
A method for attenuating a PCM signal comprising shifting said PCM signal to the lower digit side by a first number of bits to produce a first shifted signal, shifting said PCM signal to the lower digit side by a second and different number of bits to produce a second shifted signal, shifting said PCM signal to the lower digit side by a further number of bits to produce further shifted signals, adding solely said first, second and further shifted signals corresponding to said PCM signal to produce an attenuated signal, generating an integer pattern, adding said integer pattern to said attenuated signal, comparing said PCM signal with the result of said step of adding said integer pattern to said attenuated signal, and selecting the lower of said PCM signal and the result of said step of adding said integer pattern to said attenuated signal, in response to said step of comparing, for producing an attenuated output PCM signal.
Claim 6
Independent Claim
159 words
A method for attenuating a PCM signal comprising shifting said PCM signal to the lower digit side by a first number of bits to produce a first shifted signal, shifting said PCM signal to the lower digit side by a second and different number of bits to produce a second shifted signal, shifting said PCM signal to the lower digit side by a further number of bits to produce further shifted signals, adding solely said first, second and further shifted signals corresponding to said PCM signal to produce an attenuated signal, generating an integer pattern, adding said integer pattern to said attenuated signal, comparing said PCM signal with the result of said step of adding said integer pattern to said attenuated signal, and selecting the lower of said PCM signal and the result of said step of adding said integer pattern to said attenuated signal, in response to said step of comparing, for producing an attenuated output PCM signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-18 | 1980-07-19 | 1981-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-18 | 1984-07-19 | 1985-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-18 | 1988-07-19 | 1989-01-18 | $7700.00 | Window Closed / Lapsed |