Pulse code modulation code conversion

Claim 2

Apparatus for converting an input code modulation code word encoded according to a first companding law into an output pulse code modulation code word encoded according to a second companding law wherein the input word includes a segment code and a position code comprising: means for decoding the segment code; means responsive to signals from said decoding means for selectively arithmetically combining the input code word with a one at a selected bit position thereby producing an altered code word including an altered segment code and an altered position code, wherein said means for combining includes means for propagating internal arithmetic signals; control means responsive to signals from said decoding means and said combining means for producing left-shift and right-shift signals; means responsive to the left-shift signal for selectively shifting a portion of said altered position code to the left; means responsive to the right-shift signal for selectively shifting a portion of said altered position code to the right.

Claim 3

Code conversion apparatus as set forth in claim 1 wherein: said means for arithmetically combining comprises an adder including means for propagating internal carry signals; said control means comprises means for producing said left-shift signal in response to a selected segment code being decoded by said decoding means, and means for detecting a change occurring in the low order bit of the altered segment code as a result of arithmetically combining in said adder and for producing said right-shift signal in response thereto.

Claim 4

Code conversion apparatus as set forth in claim 2 wherein: said means for detecting and for producing comprises means for comparing the low order bit of the segment code of the input word with the low order bit of the altered segment code of the altered code word.

Claim 5

Code conversion apparatus as set forth in claim 2 wherein: said means for detecting and for producing comprises means for sensing the presence of a carry signal propagating within said adder from the high order bit of the altered position code to the low order bit position of the altered segment code.

Claim 6

Code conversion apparatus as set forth in claim 1 wherein: said means for arithmetically combining comprises a subtractor including means for propagating internal borrow signals, and said control means coMprises: means for producing said right-shift signal in response to a selected segment code being decoded by said decoding means, means for detecting a change occurring in the low order bit of the altered segment code as a result of arithmetically combining in said subtractor, and means for producing said left-shift signal in response to said means for detecting and in response to one of a plurality of selected segment codes being decoded by said decoding means.

Claim 7

Code conversion apparatus as set forth in claim 5 wherein: said means for detecting comprises means for comparing the low order bit of the segment code of the input word with the low order bit of the altered segment code of the altered code word.

Claim 8

Code conversion apparatus as set forth in claim 5 wherein: said means for detecting comprises means for sensing the presence of a borrow signal propagating from the high order bit position of the altered position code to the low order bit position of the altered segment code.

Claim 9

A digital code converter for re-encoding a pulse code modulation code word comprising a segment code designated by the bits ABC and a position code designated by the bits WXYZ comprising: a decoder which operates on bits ABC to produce an output on one of five output leads according to the values of ABC ranging from 000 to 100; an OR gate for producing an output when the decoder produces an output on either one of two leads according to the values of ABC equal to 000 or 001; a seven-stage binary adder to which is applied an addend ABCWXYZ and an augend comprising the output from the OR gate and three of the five output leads from the decoder applied to the low order stages of the adder to produce the sum A''B''C''W''X''Y''Z'', means for detecting a carry propagating from the high order bit W of the input position code to the low order bit C'' of the incremented segment code; means for shifting the bits W''X''Y''Z'' one bit position to the left thereby producing the bits W''''X''''Y''''Z'''' in response to an output from the decoder corresponding to the segment code ABC equal to 000; and means for shifting the bits W''''X''''Y''''Z'''' one bit position to the right in response to said detecting means.

Claim 10

A digital code converter for re-encoding a pulse code modulation code word comprising a segment code designated by the bits ABC and a position code designated by the bits WXYZ comprising: a decoder which operates on bits ABC to produce an output on one of five output leads according to the values of ABC ranging from 000 to 100; an OR gate for producing an output when the decoder produces an output on either one of two leads according to the values of ABC equal to 000 or 001; a seven-stage binary adder to which is applied an addend ABCWXYZ and an augend comprising the output from the OR gate and three of the five output leads from the decoder applied to the low order stages of the adder to produce the sum A''B''C''W''X''Y''Z'', means for detecting a carry propagating from the high order bit W of the input position code to the low order bit C'' of the incremented segment code; means for shifting the bits W''X''Y''Z'' one bit position to the left thereby producing the bits W''''X''''Y''''Z'''' in response to an output from the decoder corresponding to the segment code ABC equal to 000; and means for shifting the bits W''''X''''Y''''Z'''' one bit position to the right in response to said detecting means.

Claim 11

A digital code converter as set forth in claim 8 wherein said converter operates on an input code word encoded according to a mid-riser companding law and said means for shifting the bits W''X''Y''Z'' to the left includes means for inserting a one into the low order bit position vacated by the shift.

Claim 12

A digital code converter as set forth in claim 8 wherein said converter operates on an input code word encoded according to a mid-tread companding law and said means for shifting the bits W''X''Y''Z'' to the left includes means for inserting a zero into the low order bit position vacated by the shift.

Claim 13

A digital code converter for re-encoding a pulse code modulation code word comprising a segment code designated by the bits ABC and a position code designated by the bits WXYZ comprising: a decoder which operates on bits ABC to produce an output on one of five output leads according to the values of ABC ranging from 000 to 100; an OR gate for producing an output when the decoder produces an output on either one of two leads according to the values of ABC equal to 010 or 011; a seven-stage binary subtractor to which is applied an minuend ABCWXYZ and a subtrahend comprising the outputs on the five output leads from the decoder applied to the low-order stages of the subtractor to produce the difference bits A''B''C''W''X''Y''Z''; means for detecting a borrow propagating from the high order bit W of the input position code to the low order bit C'' of the decremented segment code; means for shifting the three bits X''Y''Z'' one bit position to the left thereby producing the bits X''''Y''''Z'''' in response to an output from the OR gate and in response to said detecting means; and means for shifting the four bits W''X''''Y''''Z'''' one bit position to the right in response to an output from the decoder corresponding to the segment code ABC equal to 000.

Claim 14

A digital code converter for re-encoding a pulse code modulation code word comprising a segment code designated by the bits ABC and a position code designated by the bits WXYZ comprising: a decoder which operates on bits ABC to produce an output on one of five output leads according to the values of ABC ranging from 000 to 100; an OR gate for producing an output when the decoder produces an output on either one of two leads according to the values of ABC equal to 010 or 011; a seven-stage binary subtractor to which is applied an minuend ABCWXYZ and a subtrahend comprising the outputs on the five output leads from the decoder applied to the low-order stages of the subtractor to produce the difference bits A''B''C''W''X''Y''Z''; means for detecting a borrow propagating from the high order bit W of the input position code to the low order bit C'' of the decremented segment code; means for shifting the three bits X''Y''Z'' one bit position to the left thereby producing the bits X''''Y''''Z'''' in response to an output from the OR gate and in response to said detecting means; and means for shifting the four bits W''X''''Y''''Z'''' one bit position to the right in response to an output from the decoder corresponding to the segment code ABC equal to 000.