Patent US3482568A successfully refreshed from Google Patents.
Patent US4003036A successfully refreshed from Google Patents.
US4003036A
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Single IGFET memory cell with buried storage element
Assignee: American Microsystems Holding Corp
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Filing: 1975-10-23
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Granted: 1977-01-11
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Expires: 1995-10-23
Abstract
Abstract A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively thin diffusion of N material spaced directly above the buried layer, forming a recess that passes through the thin N layer and the epitaxial layer into the thicker buried N layer, and thereafter forming a gate within the recess.
Inventors
- 👤 Fredrick Benjamin Jenne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/30; H10B12/34; H10D; H10D30/00; H10D30/60; H10D30/63; H10D84/00; H10D84/80; H10D84/811; H10D84/813; H10W; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/037; Y10S148/051; Y10S148/053; Y10S148/168
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
118 words
In a semiconductor memory device a single transistor cell comprising: a substrate of low resistivity semiconductor material of a preselected polarity; an epitaxial layer on said substrate having the same polarity as said substrate; a first region of material buried within said substrate and having the opposite polarity therefrom; a second region of material within said epitaxial layer having the same polarity as and spaced upwardly from said first region; a gate means located within a recess on said device, said recess extending downwardly from its upper surface through said second region and into said first region, said gate means extending between said first and second regions; and conductive contact means covering said gate means within said recess.
Claim 2
Dependent Claim
118 words
In a semiconductor memory device a single transistor cell comprising: a substrate of low resistivity semiconductor material of a preselected polarity; an epitaxial layer on said substrate having the same polarity as said substrate; a first region of material buried within said substrate and having the opposite polarity therefrom; a second region of material within said epitaxial layer having the same polarity as and spaced upwardly from said first region; a gate means located within a recess on said device, said recess extending downwardly from its upper surface through said second region and into said first region, said gate means extending between said first and second regions; and conductive contact means covering said gate means within said recess.
Claim 3
Dependent Claim
21 words
The cell as described in claim 1 wherein said first and second regions and said gate means form an IGFET device.
Claim 4
Dependent Claim
19 words
The cell as described in claim 1 wherein said epitaxial layer has a substantially higher resistivity than said substrate.
Claim 5
Dependent Claim
15 words
The cell as described in claim 1 wherein said recess is V-shaped in cross section.
Claim 6
Dependent Claim
29 words
The cell as described in claim 1 wherein said recess has an inverse pyramidial shape and said gate means extends along at least one sloping side of said recess.
Claim 7
Dependent Claim
47 words
The cell as described in claim 1 including an out diffused region extending within said epitaxial layer adjacent its interface with said substrate and over said buried first region, said out diffused region having an impurity concentration less than said substrate and greater than said epitaxial layer.
Claim 8
Dependent Claim
26 words
The cell as described in claim 1 wherein said first region comprises a combined source region and storage capacitor and extends slightly into said epitaxial layer.
Claim 9
Dependent Claim
28 words
The cell as described in claim 1 wherein said second region is thinner than said first region and comprises the drain of a single MOSFET for the cell.
Claim 10
Dependent Claim
33 words
The cell as described in claim 1 wherein said second region is extended from one side of said recess to form an interconnecting conductive path adapted to be connected to a contact means.
Claim 11
Dependent Claim
136 words
A single IGFET cell for a semiconductor memory device comprising: a substrate of P-type semiconductor material of a predetermined impurity concentration; an epitaxial layer of P material on said substrate having a lower impurity concentration and therefore a higher resistivity than said substrate material; a first region of N type material buried within said substrate; a second region of N type material within said epitaxial layer and spaced directly above said buried first region; gate means located within a recess of said device that extends downwardly from its upper surface through said second region and into said first region, said gate means extending between said first and second N regions; a non-conductive layer covering said epitaxial layer and said second region and surrounding said recess; and conductive contact means covering said gate means within said recess.
Claim 12
Dependent Claim
136 words
A single IGFET cell for a semiconductor memory device comprising: a substrate of P-type semiconductor material of a predetermined impurity concentration; an epitaxial layer of P material on said substrate having a lower impurity concentration and therefore a higher resistivity than said substrate material; a first region of N type material buried within said substrate; a second region of N type material within said epitaxial layer and spaced directly above said buried first region; gate means located within a recess of said device that extends downwardly from its upper surface through said second region and into said first region, said gate means extending between said first and second N regions; a non-conductive layer covering said epitaxial layer and said second region and surrounding said recess; and conductive contact means covering said gate means within said recess.
Claim 13
Dependent Claim
44 words
The IGFET cell according to claim 10 including an intermediate layer of P material between said substrate and said epitaxial layer and covering said first N region, said intermediate layer having an impurity concentration less than said substrate and greater than said epitaxial layer.
Claim 14
Dependent Claim
42 words
The IGFET cell according to claim 10 wherein said recess has a V-shape in a cross section taken perpendicular to the surface of the epitaxial layer, said first region forming a source and said second region forming a drain for the IGFET.
Claim 15
Dependent Claim
186 words
A semiconductor read/write memory device comprising: a substrate of low resistivity semiconductor material of a preselected polarity; an epitaxial layer on said substrate having the same polarity but a higher resistivity than said substrate; an array of memory cells on said substrate comprising a plurality of spaced apart first regions of material buried within said substrate and having the opposite polarity therefrom; a plurality of second regions of material within said epitaxial layer each having the same polarity as and spaced upwardly from a said first region; a plurality of gate means for each cell, each gate means being located within a recess on said device, each said recess extending downwardly from the upper surface of said epitaxial layer through a said second region and into a said first region, and thus extending between a pair of said first and second regions; conductive contact means covering said gate means within each said recess; first conductive means interconnecting said contact means to form address lines for said memory device; and second conductive means interconnecting said second regions of said cells to form bit lines for said device.
Claim 16
Dependent Claim
186 words
A semiconductor read/write memory device comprising: a substrate of low resistivity semiconductor material of a preselected polarity; an epitaxial layer on said substrate having the same polarity but a higher resistivity than said substrate; an array of memory cells on said substrate comprising a plurality of spaced apart first regions of material buried within said substrate and having the opposite polarity therefrom; a plurality of second regions of material within said epitaxial layer each having the same polarity as and spaced upwardly from a said first region; a plurality of gate means for each cell, each gate means being located within a recess on said device, each said recess extending downwardly from the upper surface of said epitaxial layer through a said second region and into a said first region, and thus extending between a pair of said first and second regions; conductive contact means covering said gate means within each said recess; first conductive means interconnecting said contact means to form address lines for said memory device; and second conductive means interconnecting said second regions of said cells to form bit lines for said device.
Claim 17
Dependent Claim
37 words
The memory device of claim 13 wherein said first and second regions and said gate means of each said cell form an active IGFET and said first region also forms a buried storage capacitor for the cell.
Claim 18
Dependent Claim
30 words
The memory device of claim 14 wherein said substrate is P-type semiconductor of a predetermined impurity concentration and said epitaxial layer is also P material having a lower impurity concentration.
Claim 19
Dependent Claim
43 words
The memory device of claim 15 including an intermediate layer of P material between said substrate and said epitaxial layer and covering said first N region, said intermediate layer having an impurity concentration less than said substrate and greater than said epitaxial layer.
Claim 20
Dependent Claim
25 words
The memory device of claim 14 wherein each said active IGFET is formed on the sloped walls of a recess having a V-shaped cross section.
References Cited (Backward Citations)
US3787822A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |