Circulating shift register incrementer/decrementer

Claim 1

A circuit for incrementing and decrementing coded digits of digital data in response to a clock signal and timed control signals, each digit having a plurality of bits and stored in a circulating shift register memory, said circuit comprising: input gating means coupled to the circulating shift register memory for producing a first output signal in response to the data and first and second control signals; clocked switching means coupled to the input gating means for producing a second output signal in response to the first output signal, the clock signal and a third control signal, said clock signal being at approximately the same rate as the rate at which data is received by the input gating means; and output gating means coupled to the the input gating means and the clocked switching means for producing coded bits of digital data incremented with respect to the data received by the input gating means, in response to the first and second output signals and the second control signal, said incremented data being produced when the first and second control signals are logic zero for all bits of the digit, and the third control signal is logic one during the first bit of the digit.