Electronic calculator utilizing delay line storage and interspersed serial code

Claim 1

A calculator circuit for performing arithmetic operations on signals representing binary coded input numbers and for producing output signals representing the result of said arithmetic operations, comprising, in combination: a. a dynamic pulse storage loop including a pulse delay line, input means for applying a train of pulses representing binary coded numbers to one end of said delay line, output means for receiving said train of pulses at the other end of said delay line, and feedback means coupled between the input and output means of said delay line for continuously recirculating said train of pulses through said delay line; b. timing circuit means coupled to the input means and output means of said pulse storage loop for defining an interspersed serial code in which the individual bits of at least two binary coded numbers are interspersed with each other in said train of pulses, each bit of each binary number being adjacent in the pulse train sequence to the corresponding bit of a different binary number, whereby the consecutive bits of each binary number are separated from each other in the pulse train sequence and are interspersed among the individual bits of other binary numbers; c. shift register means coupled to the input means and output means of said pulse storage loop and to said timing means for introducing binary coded numbers into said pulse storage loop in accordance with said interspersed serial code and for extracting individual binary coded numbers from the interspersed serial pulses circulating in said pulse storage loop; d. said timing circuit incorporating means for operating said shift register at a shift frequency which is substantially lower than the bit rate of said pulse storage loop and which is synchronized with said bit rate in accordance with said interspersed serial code; e. means coupled to said shift register for receiving binary coded numbers from said shift register and performing arithmetic operations on such binary coded numbers and for shifting signals representing the result of said arithmetic operations into said shift register; f. means coupled to said shift register for applying input signals thereto representing binary coded input numbers upon which arithmetic operations are to be performed; and g. means coupled to said shift register for receiving output signals therefrom representing the result of said arithmetic operations.