Patent US3997367A successfully refreshed from Google Patents.
US3997367A
Expired / Lapsed
US
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Method for making transistors
Assignee: AT&T Inc
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Filing: 1975-11-20
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Granted: 1976-12-14
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Expires: 1995-11-20
Abstract
Abstract Submicron plasma trimming of a patterened resist material is combined with ion implantation techniques to achieve submicron control of lateral doping profiles. This makes possible the high-yield fabrication of, for example, bipolar microwave transitors of the self-aligned-emitter type. The basic technique can also be supplied to the fabrication of high performance insulted-gate field-effect transistors, junction-gate field-effect transistors and Schottky-barrier field-effect transistors.
Inventors
- 👤 Leopoldo Dy Yau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:35
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10P30/00; H10P30/20; H10P30/22; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287; Y; Y10; Y10S; Y10S148/00; Y10S148/131; Y10S438/00; Y10S438/942; Y10S438/948
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
90 words
A method for making a semiconductor device comprising the steps of forming a prescribed resist pattern on a semiconductor body of one conductivity type, establishing regions of a specified conductivity type in portions of said body not masked by said resist pattern whereby said regions are spaced apart laterally in said body by a distance approximately equal to the width of said resist pattern, and trimming said resist pattern by a predetermined amount to reduce the width thereof thereby to provide a mask member for subsequent processing of said device.
Claim 2
Independent Claim
90 words
A method for making a semiconductor device comprising the steps of forming a prescribed resist pattern on a semiconductor body of one conductivity type, establishing regions of a specified conductivity type in portions of said body not masked by said resist pattern whereby said regions are spaced apart laterally in said body by a distance approximately equal to the width of said resist pattern, and trimming said resist pattern by a predetermined amount to reduce the width thereof thereby to provide a mask member for subsequent processing of said device.
Claim 3
Independent Claim
131 words
A method for making a semiconductor device comprising the steps of forming a first layer on a semiconductor body of one conductivity type, forming a prescribed resist pattern on said first layer, establishing regions of a specified conductivity type in portions of said body not masked by said resist pattern whereby said regions are spaced apart laterally in said body by a distance approximately equal to the width of said resist pattern, trimming said resist pattern in an oxidizing plasma by a predetermined amount to reduce the width thereof, removing those portions of said first layer that are not masked by said trimmed resist pattern, and removing said resist pattern thereby leaving on said body a portion of said first layer whose width corresponds to the width of said trimmed resist.
Claim 4
Independent Claim
131 words
A method for making a semiconductor device comprising the steps of forming a first layer on a semiconductor body of one conductivity type, forming a prescribed resist pattern on said first layer, establishing regions of a specified conductivity type in portions of said body not masked by said resist pattern whereby said regions are spaced apart laterally in said body by a distance approximately equal to the width of said resist pattern, trimming said resist pattern in an oxidizing plasma by a predetermined amount to reduce the width thereof, removing those portions of said first layer that are not masked by said trimmed resist pattern, and removing said resist pattern thereby leaving on said body a portion of said first layer whose width corresponds to the width of said trimmed resist.
Claim 5
Dependent Claim
22 words
A method as in claim 2 wherein said establishing step comprises ion implanting regions of the opposite conductivity type in said body.
Claim 6
Dependent Claim
38 words
A method as in claim 3 wherein the width of said resist pattern is trimmed by an amount that corresponds to the lateral movement of said implanted regions toward each other that occurs during fabrication of said device.
Claim 7
Dependent Claim
16 words
A method as in claim 4 wherein said first layer comprises a layer of silicon nitride.
Claim 8
Dependent Claim
15 words
A method as in claim 4 wherein said first layer comprises a layer of polysilicon.
Claim 9
Dependent Claim
27 words
A method as in claim 3 further including the step of ion implanting buffer regions in portions of said body not masked by said trimmed resist pattern.
Claim 10
Dependent Claim
16 words
A method as in claim 7 wherein said first layer comprises a layer of silicon nitride.
Claim 11
Dependent Claim
35 words
A method as in claim 8 further including the step of growing a layer of silicon dioxide on the surface portions of said device that are not covered by the remaining portion of silicon nitride.
Claim 12
Dependent Claim
48 words
A method as in claim 9 comprising the further step of removing said remaining portion of silicon nitride thereby to form a window in said silicon dioxide for access to said semiconductor body and then successively ion implanting through said window base and emitter regions in said body.
Claim 13
Independent Claim
229 words
A method of fabricating a self-aligned-emitter bipolar transistor of the type that includes a submicron-wide buffer base region interposed between inactive and active base regions, said method comprising the steps of forming a first layer on a silicon member of one conductivity type, forming a pattern of resist material on said first layer, establishing by a relatively high-dosage ion implantation an inactive base region of the opposite conductivity type in said member in regions not masked by said resist pattern, laterally trimming said resist by a predetermined amount in an oxidizing plasma, removing those portions of the first layer that are not masked by said trimmed resist, establishing by a relatively low-dosage ion implantation a region of the opposite conductivity type in said member in regions not masked by said trimmed resist pattern thereby to form a buffer base region whose lateral extent corresponds approximately to the predetermined amount trimmed from said resist, removing said resist material, growing a second layer on all the surface portions of said silicon member except for the portion masked by the remaining portion of said first layer, removing the remaining portion of said first layer, and successively forming by ion implantation base and emitter regions in said silicon member in regions not masked by said second layer whereby said buffer base region is interposed between said inactive base region and said emitter region.
Claim 14
Independent Claim
229 words
A method of fabricating a self-aligned-emitter bipolar transistor of the type that includes a submicron-wide buffer base region interposed between inactive and active base regions, said method comprising the steps of forming a first layer on a silicon member of one conductivity type, forming a pattern of resist material on said first layer, establishing by a relatively high-dosage ion implantation an inactive base region of the opposite conductivity type in said member in regions not masked by said resist pattern, laterally trimming said resist by a predetermined amount in an oxidizing plasma, removing those portions of the first layer that are not masked by said trimmed resist, establishing by a relatively low-dosage ion implantation a region of the opposite conductivity type in said member in regions not masked by said trimmed resist pattern thereby to form a buffer base region whose lateral extent corresponds approximately to the predetermined amount trimmed from said resist, removing said resist material, growing a second layer on all the surface portions of said silicon member except for the portion masked by the remaining portion of said first layer, removing the remaining portion of said first layer, and successively forming by ion implantation base and emitter regions in said silicon member in regions not masked by said second layer whereby said buffer base region is interposed between said inactive base region and said emitter region.
Claim 15
Dependent Claim
21 words
A method as in claim 11 wherein said first and second layers comprise layers of silicon nitride and silicon dioxide, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-12-14 | 1980-06-14 | 1980-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-12-14 | 1984-06-14 | 1984-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-12-14 | 1988-06-14 | 1988-12-14 | $7700.00 | Window Closed / Lapsed |