Key switch signal multiplexer circuit

Claim 2

A key input circuit comprising a plurality of key blocks each including a plurality of keys, timing pulse generator means for generating a plurality of series of sequential timing pulses of different phase connected respective to said key blocks so that each timing pulse of a respective series is applied to the input side of a respective key in each key block, the output side of each key in each key block being connected to a respective common terminal, key input circuit means for multiplexing the outputs of said common terminals in sequential time frames, and read control circuit means connected to receive the output of said key input circuit means and said plurality of series of sequential timing pulses from said timing pulse generator means for generating actuating signals designating a key which has been actuated.

Claim 3

A key input circuit as defined in claim 1 wherein said read control circuit means includes a plurality of AND gates each receiving the output of said key input circuit means and a respective one of said series of timing pulses.

Claim 4

A key input circuit as defined in claim 2, further including memory means for storing representations of said actuating signals.

Claim 5

A key input circuit as defined in claim 3, further including encoder means connected between said read control circuit means and said memory means for converting said actuating signals to a binary combination of signals representing said actuating signals.

Claim 6

A key input circuit as defined in claim 3, further including encoder means connected to the output of said memory means for converting said stored representations of said actuating signals to a binary combination of signals.

Claim 7

A key input circuit comprising: timing pulse generator means for providing a plurality of sequential timing pulses in a repetitive time frame; a first group of key switches, one terminal of each of said key switches being connected to said timing pulse generator means so as to receive a respective timing pulse of said sequential timing pulses, the other terminals of said key switches being connected in common; a second group of key switches, one terminal of each of said second group of key switches being connected to said timing pulse generator means so as to receive a respective timing pulse of said sequential timing pulses, the other terminals of said second group of key switches being connected in common; key input circuit means connected to the commonly connected terminals of said first and second groups of key switches for providing a multiplexed pulse signal in which outputs of the commonly connected terminals of said first and second groups of key switches are multiplexed in sequential time frames; and read control circuit means including a group of AND gates, each of the AND gates receiving said multiplexed pulse signal as an input thereof and also receiving a respective one of said sequential timing pulses of said timing pulse generator means as another input thereof.

Claim 8

A key input circuit comprising: timing pulse generator means for providing a plurality of sequential timing pulses in a repetitive time frame; a first group of key switches, one terminal of each of said key switches being connected to said timing pulse generator means so as to receive a respective timing pulse of said sequential timing pulses, the other terminals of said key switches being connected in common; a second group of key switches, one terminal of each of said second group of key switches being connected to said timing pulse generator means so as to receive a respective timing pulse of said sequential timing pulses, the other terminals of said second group of key switches being connected in common; key input circuit means connected to the commonly connected terminals of said first and second groups of key switches for providing a multiplexed pulse signal in which outputs of the commonly connected terminals of said first and second groups of key switches are multiplexed in sequential time frames; and read control circuit means including a group of AND gates, each of the AND gates receiving said multiplexed pulse signal as an input thereof and also receiving a respective one of said sequential timing pulses of said timing pulse generator means as another input thereof.

Claim 9

A key input circuit of claim 6, wherein said key input circuit means comprises a first and a second AND gate, said first AND gate receiving the output of the commonly connected terminals of said first group of key switches and a first series of control pulses, said second AND gate receiving the output of the commonly connected terminals of said second group of key switches and a second series of control pulses which is alternate in time with said first series of control pulses, said first and second control pulses having a duration substantially equal to said time frame, said key input circuit means further comprising an OR gate receiving outputs of said first and second AND gates and providing said multiplexed pulse signal.

Claim 10

A key input of claim 7, wherein said read control circuit means further comprises an additional AND gate which receives said multiplexed pulse signal, a selected one of said timing pulses of said timing pulse generator means and said second series of control pulses as inputs thereof.

Claim 11

In a key input circuit comprising a first, a second, a third and a fourth key switch each having a first and a second terminal, means for applying a first and a second timing pulse different in phase from each other to said first terminals of said first and second key switches, respectively, and to said first terminals of said third and fourth key switches, respectively, said second terminals of said first and second key switches being connected to a first common terminal and said second terminals of said third and fourth key switches being connected to a second common terminal, the improvement comprising key input means for multiplexing a first key signal and a second key signal appearing on said first and second common terminals, respectively, means for applying to said key input means a third and a fourth timing pulse different in phase from each other, each of said third and fourth timing pulses having pulse portions overlapping in time with that of said first and second timing pulses, but having a different pulse width therefrom, said key input means comprising means responsive to the logical products of said first and third, of said second and third, of said first and fourth and of said second and fourth timing pulses, respectively, to provide key signals at the output thereof corresponding to the key operation of said first, second, third and fourth key switches, respectively.

Claim 12

In a key input circuit comprising a first, a second, a third and a fourth key switch each having a first and a second terminal, means for applying a first and a second timing pulse different in phase from each other to said first terminals of said first and second key switches, respectively, and to said first terminals of said third and fourth key switches, respectively, said second terminals of said first and second key switches being connected to a first common terminal and said second terminals of said third and fourth key switches being connected to a second common terminal, the improvement comprising key input means for multiplexing a first key signal and a second key signal appearing on said first and second common terminals, respectively, means for applying to said key input means a third and a fourth timing pulse different in phase from each other, each of said third and fourth timing pulses having pulse portions overlapping in time with that of said first and second timing pulses, but having a different pulse width therefrom, said key input means comprising means responsive to the logical products of said first and third, of said second and third, of said first and fourth and of said second and fourth timing pulses, respectively, to provide key signals at the output thereof corresponding to the key operation of said first, second, third and fourth key switches, respectively.

Claim 13

The improvement according to claim 9, wherein a first logical gate to which the output signal of said key input means and said first timing pulse are supplied at its inputs, second logical gate to which the output signal of said key input means and said second timing pulse are supplied as its inputs and, a third logical gate to which the output signals of said first and second logical gates and said third timing pulse are supplied as its inputs.

Claim 14

The improvement according to claim 10, comprising memory means for storing the outputs of said first, second and third logical gates.

Claim 15

The improvement according to claim 9, wherein each of said third and fourth timing pulses has a pulse duration equal in time to the pulse recurrence time of each of said first and second timing pulses.