Concurrent entry preventing system

Claim 2

A concurrent entry preventing systemfor use in an electronic calculating machine comprising a keyboard having a plurality of figure keys corresponding to the decimal digits (1) to (9) arranged on said keyboard in such a manner that, in the lowermost row from left to right, the (1) to (3) figure keys are positioned; in the second row from left to right, the (4) to (6) figure keys are positioned; and in the third or topmost row from left to right, the (7) to (9) figure keys are positioned, a plurality of key contacts operatively associated with said figure keys, and means for yielding the logical product of an output signal indicative of operation of one of said figure keys bearing the odd number and an output signal indicative of operation of the other one of said figure keys bearing the even number, said logical product from said means being capable of indicating through a suitable circuit device the fact that two or more figure keys are concurrently operated erroneously.

Claim 3

A concurrent entry preventing system according to claim 1, wherein said figure keys further include a (0) figure key disposed on said keyboard at one side of the square area occupied by said (1) to (9) figure keys, said (0) figure key being construed as included in the even numbered figure keys.

Claim 4

A concurrent entry preventing system for use in an electronic calculating machine comprising a keyboard having a plurality of figure keys corresponding to the decimal digits (1) to (9) arranged on said keyboard in such a manner that, in the lowermost row from left to right, the (1) to (3) figure keys are positioned; in the second row from left to right, the (4) to (6) figure keys are positioned; and in the third or topmost row from left to right, the (7) to (9) figure keys are positioned, and a decimal point (.) key, a plurality of key contacts operatively associated with said figure keys and said decimal point key, means for yielding the logical product of an output signal indicative of operation of one of said figure keys bearing the odd number and an output signal indicative of operation of the other one of said figure keys bearing the even number, and means for yielding the logical product of an output signal indicative of operation of one of said figure keys and an output signal indicative of operation of the decimal point key, any of said two logical products from said both means being capable of indicating through a suitable circuit device the fact that at least one of said figure keys and the decimal point key or two or more of said figure keys are concurrently operated erroneously.

Claim 5

A concurrent entry preventing system for use in an electronic calculating machine comprising a keyboard having a plurality of figure keys corresponding to the decimal digits (1) to (9) arranged on said keyboard in such a manner that, in the lowermost row from left to right, the (1) to (3) figure keys are positioned; in the second row from left to right, the (4) to (6) figure keys are positioned; and in the third or topmost row from left to right, the (7) to (9) figure keys are positioned, and a decimal point (.) key, a plurality of key contacts operatively associated with said figure keys and said decimal point key, means for yielding the logical product of an output signal indicative of operation of one of said figure keys bearing the odd number and an output signal indicative of operation of the other one of said figure keys bearing the even number, and means for yielding the logical product of an output signal indicative of operation of one of said figure keys and an output signal indicative of operation of the decimal point key, any of said two logical products from said both means being capable of indicating through a suitable circuit device the fact that at least one of said figure keys and the decimal point key or two or more of said figure keys are concurrently operated erroneously.

Claim 6

A concurrent entry preventing system for use in an electronic calculating machine comprising a keyboard having a plurality of figure keys corresponding to the decimal digits (1) to (9) arranged on said keyboard in such a manner that, in the lowermost row from left to right, the (1) to (3) figure keys are positioned; in the second row from left to right, the (4) to (6) figure keys are positioned; and in the third or topmost row from left to right, the (7) to (9) figure keys are positioned, a decimal point key and a (0) figure key positioned on the keyboard adjacent to said decimal point key immediately below said lowermost row, a first means for yielding the logical product of an output signal indicative of operation of one of said figure keys bearing the odd number and an output signal indicative of operation of the other one of said figure keys bearing the even number including (0), and a second means for yielding the logical product of an output signal indicative of operation of one of said figure keys and an output siGnal indicative of operation of the decimal point key, any of said two logical products from said first and second means being capable of indicating through a suitable circuit device the fact that at least one of said figure keys and the decimal point key or two or more of said figure keys are concurrently operated in a wrong course.

Claim 7

A concurrent entry preventing system for use in an electronic calculating machine comprising a keyboard having a plurality of figure keys corresponding to the decimal digits (1) to (9) arranged on said keyboard in such a manner that, in the lowermost row from left to right, the (1) to (3) figure keys are positioned; in the second row from left to right, the (4) to (6) figure keys are positioned; and in the third or topmost row from left to right, the (7) to (9) figure keys are positioned, a decimal point key and a (0) figure key positioned on the keyboard adjacent to said decimal point key immediately below said lowermost row, a first means for yielding the logical product of an output signal indicative of operation of one of said figure keys bearing the odd number and an output signal indicative of operation of the other one of said figure keys bearing the even number including (0), and a second means for yielding the logical product of an output signal indicative of operation of one of said figure keys and an output siGnal indicative of operation of the decimal point key, any of said two logical products from said first and second means being capable of indicating through a suitable circuit device the fact that at least one of said figure keys and the decimal point key or two or more of said figure keys are concurrently operated in a wrong course.

Claim 8

A concurrent entry preventing apparatus comprising: a keyboard having a plurality of figure keys; a plurality of key switches, each including terminals and a contact, coupled to said plurality of figure keys, for providing an electric potential at one of the terminals thereof upon activation of one of said figure keys; and means, coupled to each of said key switches, for generating an output signal representative of the logical product of the potentials provided by more than one of said key switches in response to the simultaneous activation of more than one of said figure keys, said plurality of figure keys comprising a first identifiable set of figure keys and a second identifiable set of figure keys, said output signal generating means including means, responsive to the simultaneous activation of one of the keys in said first set with one of the keys in said second set, for generating said output signal.

Claim 9

A concurrent entry preventing apparatus comprising: a keyboard having a plurality of figure keys; a plurality of key switches, each including terminals and a contact, coupled to said plurality of figure keys, for providing an electric potential at one of the terminals thereof upon activation of one of said figure keys; and means, coupled to each of said key switches, for generating an output signal representative of the logical product of the potentials provided by more than one of said key switches in response to the simultaneous activation of more than one of said figure keys, said plurality of figure keys comprising a first identifiable set of figure keys and a second identifiable set of figure keys, said output signal generating means including means, responsive to the simultaneous activation of one of the keys in said first set with one of the keys in said second set, for generating said output signal.

Claim 10

An apparatus according to claim 5, wherein said output signal generating means comprises a diode matrix, having a pair of orthogonal connection branches, one orthogonal branch of which is connected to said key switches, and the other orthogonal branch of which is connected to a first reference potential.

Claim 11

An apparatus according to claim 6, wherein said output signal generating means further comprises a first AND gate having a pair of inputs, a first of which is connected to each key switch of said first set and the second of which is connected to each key switch of said second set.

Claim 12

An apparatus according to claim 7, further including a plurality of reduction AND gates, respectively connected to one of said orthogonal branches and one of the inputs of each of which being connected to a source of timing signals, for partially energizing each of said reduction AND gates in response to the application of said timing signals, and whose outputs are connected to a OR gate for logically combining the outputs of each of said reduction AND gates.

Claim 13

An apparatus according to claim 5, wherein said plurality of figure keys comprises first and second additional figure keys separate from said first and second sets of figure keys and wherein said output signal generating means further comprises means, responsive to the simultaneous activation of one of the figure keys in one of said first and second sets and one of the figure keys of one of said first and second additional keys, for generating said output signal.

Claim 14

An apparatus according to claim 9, wherein said output signal generating means comprises a diode matrix, having a pair of orthogonal connection branches, one orthogonal branch of which is connected to said key switches, and the other orthogonal branch of which is connected to a source of reference potential.

Claim 15

An apparatus according to claim 10, wherein said output signal generating means further comprises a first AND gate having a pair of inputs, a first of which is connected to each key switch of said first set and the second of which is connected to each key switch of said second set, a second AND gate, having a pair of inputs, a first of which is connected to said first additional key switch and the second of which is connected to one key switch of one of said sets, a third AND gate, having a pair of inputs, a first of which is connected to each key switch of each of said sets and a second of which is connected to said second additional key switch, and means for logically combining the outputs of each of said first, second and third AND gates.

Claim 16

An apparatus according to claim 11, further including a plurality of reduction AND gates, respectively connected to one of said orthogonal branches and each of which is connected to a source of timing signals for partially energizing each of said reduction AND gates in response to the application of said timing signal, and an output OR gate for logicallly combining the outputs of each of said reduction AND gates.

Claim 17

An apparatus according to claim 12, further comprising a key board, on which said plurality of keys are arranged, said first and second sets of keys being arranged in alternate orthogonal relationship with respect to each other and said additional figure keys being arranged immediately adjacent with respect to each other and said sets of keys.