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US3987313A Expired / Lapsed US ⏱️ 0.0 years remaining

Arrangement for the generating of pulse trains for charge-coupled circuits

Assignee: Siemens AG
•
Filing: 1974-12-30
•
Granted: 1976-10-19
•
Expires: 1994-12-30
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Abstract

Abstract An arrangement for generating pulse trains for charged-coupled circuits employs a plurality of series-connected master-slave JK flip-flop circuits in which a Q output of a flip-flop circuit is connected to a J input of the following flip-flop circuit and in which a terminal for obtaining the generated timing pulses is provided at each Q output of a flip-flop circuit. A pulse train input for providing timing pulses to the flip-flop circuits and for each flip-flop circuit an NAND gate is provided whose output is connected to the clear input of the flip-flop circuit. One input of the NAND gate is connected to the timing pulse input line and another input is connected to a Q output of the following flip-flop circuit, except for the last flip-flop circuit in which the other input of the NAND gate associated therewith is connected to the Q output of the first flip-flop circuit. The K inputs of the flip-flop circuits are connected to a fixed potential, preferably a common connection to ground, and the individual flip-flop circuits may be additionally set by way of the clear inputs. In one embodiment the arrangement is constructed for two-phase operation and in another embodiment the arrangement is constructed for three-phase operation.

Inventors

  • 👤 Hans-Joerg Pfleiderer
  • 👤 Karl Knauer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 07:20
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; H03K5/151; H03K5/1515

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 208 words
An arrangement for generating pulse trains for charge coupled circuits, comprising: a plurality of JK master-slave flip-flop stages each including a J input, a K input, a trigger input, a clear input and a Q output, said stages connected in a series chain in which the Q output of each stage preceding the last stage of the chain is connected to the J input of the following stage of the chain; a timing pulse train input connected to said trigger input of each stage for supplying timing pulses of a predetermined pulse width thereto; and a plurality of NAND gates each including an output connected to said clear input of a respective stage, a first input connected to said timing pulse train input, and a second input connected to said Q output of the following stage with said second input of the NAND gate associated with the last stage connected to said Q output of the first stage of the chain, each of said K inputs connected to a common reference potential, wherein said stages are responsive to set conditions at said clear inputs to generate phase output pulses at said Q outputs which overlap by said predetermined width of the timing pulses applied to said NAND gates.
Claim 2
Dependent Claim 208 words
An arrangement for generating pulse trains for charge coupled circuits, comprising: a plurality of JK master-slave flip-flop stages each including a J input, a K input, a trigger input, a clear input and a Q output, said stages connected in a series chain in which the Q output of each stage preceding the last stage of the chain is connected to the J input of the following stage of the chain; a timing pulse train input connected to said trigger input of each stage for supplying timing pulses of a predetermined pulse width thereto; and a plurality of NAND gates each including an output connected to said clear input of a respective stage, a first input connected to said timing pulse train input, and a second input connected to said Q output of the following stage with said second input of the NAND gate associated with the last stage connected to said Q output of the first stage of the chain, each of said K inputs connected to a common reference potential, wherein said stages are responsive to set conditions at said clear inputs to generate phase output pulses at said Q outputs which overlap by said predetermined width of the timing pulses applied to said NAND gates.
Claim 3
Dependent Claim 24 words
An arrangement according to claim 1, comprising an inverter connected to said timing pulse train input for providing the timing pulses from inverted pulses.
Claim 4
Dependent Claim 23 words
An arrangement according to claim 1, wherein said plurality of JK master-slave flip-flop stages comprises three stages for pulse-train generation for three-phase operation.
Claim 5
Dependent Claim 50 words
An arrangement according to claim 3, comprising a NOR gate including an output connected to said J input of the first stage of the chain, a first input connected to said Q output of the first stage and a second input connected to said Q output of the second stage.
Claim 6
Dependent Claim 24 words
An arrangement according to claim 1, wherein said plurality of JK master-slave flip-flop stages comprises two stages for pulse train generation for two-phase operation.
Claim 7
Dependent Claim 23 words
An arrangement according to claim 5, wherein the first stage includes a Q output connected to the J input of the first stage.

References Cited (Backward Citations)

US3471790A Cited
US3541356A Cited
US3518552A Cited
US3745535A Cited
US3786276A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-10-19 1980-04-19 1980-10-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-10-19 1984-04-19 1984-10-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-10-19 1988-04-19 1988-10-19 $7700.00 Window Closed / Lapsed

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