Abstract An improved communication apparatus for communicating between a first object and a second object wherein the first object includes apparatus for generating and transmitting a transmit signal and the second object includes apparatus for receiving the transmit signal and providing an emitted signal in response thereto, the emitted signal having a frequency coherently related to the frequency of the received transmit signal. The second object also includes an apparatus for encoding an identifying code having a unique code format wherein the beginning and the end of the code format are identifiable, the first object including apparatus for receiving the encoded emitted signal, identifying the code format encoded therein and determining the received emitted signal represents a valid code format. In one aspect, the first object apparatus receives encoded emitted signals via two receivers, identifies the code format encoded in the first-received and the second-received encoded emitted signals, determines that each received signal has a valid format encoded therein and compares the code formats encoded in the first-received and the second-received emitted signals to determine the signals were emitted via the same second object. In one operational embodiment, the communication apparatus transmits a transmit signal and receives encoded emitted signals from a moving second object in response to the received transmit signal at a first position and a second position of the second object, the first and the second received encoded emitted signals being determined to represent a valid predetermined code format and it being determined that the received code formats are identical, the speed and direction of the moving object being determined in response to such valid determinations, the code format encoded in the received emitted signals being compared with predetermined identification code formats for locating predetermined second objects. The first object apparatus also generates and transmits a modulation signal, the second object apparatus including apparatus for detecting the modulation signal via a pulse width detector and providing an output indication in response thereto. In one particular operational embodiment, the first object apparatus is utilized to detect and monitor vehicle traffic, each vehicle (second object) having apparatus for receiving the transmit signal and providing the encoded emitted signal in response thereto, and for receiving the modulation signal and providing a driver-perceivable output indication in response thereto.
Apparatus for providing an output signal having a binary code of length p bits cyclically encoded therein, comprising: a clock providing clock pulses; a first shift register receiving the clock pulses, the first shift register having P digital shift register stages containing the code bits of the binary code with the last stage of the first shift register providing an output signal having the binary code encoded therein and the first stage of the first shift register receiving the output signal from the last stage of the first shift register, the first shift register clocking the code bit within each stage into the next successive stage with the code bit in the last stage being clocked into the first stage in response to a received clock pulse; a second shift register receiving the clock pulses, the second shift register having P digital shift register stages containing the binary code with the last stage of the second shift register providing an output signal and the first stage of the second shift register receiving the output signal from the last stage of the second shift register, the second shift register clocking the code bit within each stage into the next successive stage, with the code bit in the last stage being clocked into the first stage, in response to a received clock pulse; a gate receiving the output signal from the last stage of the first shift register and the last stage of the second shift register, respectively, and providing an output signal in response to a difference between the signal received from the last stage of the first shift register and the signal received from the last stage of the second shift register indicating a malfunction of one of the first and second shift registers; and means for determining the repeatability of the binary code encoded in the output signal provided by the last stage of the first shift register comprising: a channel shift register receiving the encoded signal and the clock pulses, the channel shift register having (P + 1) digital shift register stages and at least the first and last stages of the channel shift register providing output signals corresponding to the code bits therein, the channel shift register clocking each successive code bit of the encoded signal into the first stage and clocking the code bit within each stage into the next successive stage in response to a received clock pulse; a gate receiving the output signals from the first and last digital shift register stages and providing a reset signal in response to a difference between the signal received from the first digital shift register stage and the signal received from the last digital shift register stage; and, an R-pulse counter receiving the clock pulses and the reset signal, the R-pulse counter counting the clock pulses and producing an output signal indicative of the repeatability of the binary code in response to counting R clock pulses, where R is a predetermined integer multiple of P, the R-pulse counter being reset in response to a received reset signal.
Claim 2
Dependent Claim
510 words
Apparatus for providing an output signal having a binary code of length p bits cyclically encoded therein, comprising: a clock providing clock pulses; a first shift register receiving the clock pulses, the first shift register having P digital shift register stages containing the code bits of the binary code with the last stage of the first shift register providing an output signal having the binary code encoded therein and the first stage of the first shift register receiving the output signal from the last stage of the first shift register, the first shift register clocking the code bit within each stage into the next successive stage with the code bit in the last stage being clocked into the first stage in response to a received clock pulse; a second shift register receiving the clock pulses, the second shift register having P digital shift register stages containing the binary code with the last stage of the second shift register providing an output signal and the first stage of the second shift register receiving the output signal from the last stage of the second shift register, the second shift register clocking the code bit within each stage into the next successive stage, with the code bit in the last stage being clocked into the first stage, in response to a received clock pulse; a gate receiving the output signal from the last stage of the first shift register and the last stage of the second shift register, respectively, and providing an output signal in response to a difference between the signal received from the last stage of the first shift register and the signal received from the last stage of the second shift register indicating a malfunction of one of the first and second shift registers; and means for determining the repeatability of the binary code encoded in the output signal provided by the last stage of the first shift register comprising: a channel shift register receiving the encoded signal and the clock pulses, the channel shift register having (P + 1) digital shift register stages and at least the first and last stages of the channel shift register providing output signals corresponding to the code bits therein, the channel shift register clocking each successive code bit of the encoded signal into the first stage and clocking the code bit within each stage into the next successive stage in response to a received clock pulse; a gate receiving the output signals from the first and last digital shift register stages and providing a reset signal in response to a difference between the signal received from the first digital shift register stage and the signal received from the last digital shift register stage; and, an R-pulse counter receiving the clock pulses and the reset signal, the R-pulse counter counting the clock pulses and producing an output signal indicative of the repeatability of the binary code in response to counting R clock pulses, where R is a predetermined integer multiple of P, the R-pulse counter being reset in response to a received reset signal.