Acquisition process in a phase-locked-loop by gated means

Claim 1

A phase-locked-loop circuit configuration for improving the acquisition process comprising: phase detector means for comparing the phase between an input signal and a feedback signal providing at its output an error signal proportional thereto; edge detector means driven by said input signal for detecting the positive edge thereof providing at its output a positive going step signal; tri-state signal conditioner means having a first input driven by said error signal from said phase detector means, and a second input driven by said positive going step signal from said edge detector means for providing at its output an error signal having three levels; loop filter means driven by said error signal having three levels for further conditioning said three level error signal; gated controlled oscillator means driven by said further conditioned three level error signal for providing an output signal that tracks said input signal, and for providing said feedback signal to said phase detector, said further conditioned three level error signal biasing said gated controlled oscillator at a point which enables said gated control oscillator to be turned on at the frequency of said input signal and at the stable null π/2 when a gating signal is present; π/2 delayer means driven by said positive going step voltage from said edge detector means for delaying thereof, said delayed positive going step signal gating said gated controlled oscillator on; said gated controlled oscillator locking up at said stable null π/2 and at said frequency of said input signal and eliminating the statistical nature of said acquisition process and decreasing the lock-up-time of the loop.