Pulse circuits

Claim 2

A high-speed pulse detection circuit comprising an input terminal to which a pulse may be applied, input means connected to the input terminal for providing a short discharge time when a pulse is applied to the input terminal and a long charge time when the pulse is terminated, a Schmitt trigger stage having a first and a second input and an output, said first input being connected to said input means, a second stage having a reset input, an input connected to said output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and means connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state by the application of a pulse to the input terminal of a duration sufficient to provide a voltage at said first input equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 3

A circuit as claimed in claim 1 in which the second stage is a gate operable to maintain the voltage level of the input of the first input of the Schmitt trigger stage below its second threshold level.

Claim 4

A circuit as claimed in claim 1 wherein said input means for providing said short discharge time and said long charge time includes a gate connected to the input terminal and a resistance-capacitance connected between the output of the gate and the first input, said input means being operable to ensure that the duration of an input pulse is extended to ensure operation of the high speed pulse detection circuit.

Claim 5

A high speed priority circuit comprising at least one first input terminal to which a first pulse signal may be applied, at least one other input terminal to which other pulse signals may be applied and means for ensuring that said first pulse signal is given priority over said other pulse signals, said means including input means connected to the first input terminal for providing a short discharge time when a pulse is applied to said first input terminal and a long charge time when the pulse is terminated, a Schmitt trigger stage having a first and a second input and an output, said first input being connected to said input means, a second stage having a reset input, an input connected to said output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and output means connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state by the application of a pulse to the input terminal of a duration sufficient to provide a voltage at said one input equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 6

A high speed priority circuit comprising at least one first input terminal to which a first pulse signal may be applied, at least one other input terminal to which other pulse signals may be applied and means for ensuring that said first pulse signal is given priority over said other pulse signals, said means including input means connected to the first input terminal for providing a short discharge time when a pulse is applied to said first input terminal and a long charge time when the pulse is terminated, a Schmitt trigger stage having a first and a second input and an output, said first input being connected to said input means, a second stage having a reset input, an input connected to said output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and output means connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state by the application of a pulse to the input terminal of a duration sufficient to provide a voltage at said one input equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 7

A priority circuit as claimed in claim 4 wherein said means for providing said short discharge time and said long charge time includes a gate connected to the input terminal and a resistance-capacitance circuit connected between the output of the gate and the first input, said input means being operable to ensure that the duration of an input pulse is extended to ensure operation of the circuit, said second stage being operable to maintain the input of the Schmitt trigger stage at a voltage below its second threshold level and said means for ensuring priority further includes at least one other bistable loop having an input connected to said other input terminal and an output connected to a second output terminal and gate means connected between the output of the first and the other bistable loop and said second output terminal for gating the output thereto in accordance with the priority of said first and said second pulse signals.

Claim 8

A high speed priority circuit as set forth in claim 4 wherein said high speed detection circuit further includes input signal transfer means connected to each said second input terminal for passing said other pulse signal and being operably connected to said high speed detection circuit such that every first input signal at said first terminal is compared with every other input signal.

Claim 9

A high speed priority circuit as set forth in claim 4 comprising a plurality of inputs and including n-1 of said pulse detection circuits, where n is the number of pulse inputs, for comparing every input to said priority circuit with every other input.

Claim 10

A high speed pulse detection circuit comprising an input terminal to which a pulse may be applied, means for delaying the trailing edge of any such pulse including a serially connected resistor and a capacitor connected between a voltage source and ground, the junction of said resistor capacitor being connected to the input terminal, said means providing a short discharge time when a pulse is applied to the input terminal and a long charge time when the pulse is terminated, a Schmitt trigger stage having a first and a second input, said first input being connected to the junction of the resistor and capacitor, a second stage having a reset input, an input connected to the output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and an output terminal connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state by the application of a pulse to the input terminal of a duration sufficient to discharge the capacitor to a voltage equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 11

A high speed pulse detection circuit comprising an input terminal to which a pulse may be applied, means for delaying the trailing edge of any such pulse including a serially connected resistor and a capacitor connected between a voltage source and ground, the junction of said resistor capacitor being connected to the input terminal, said means providing a short discharge time when a pulse is applied to the input terminal and a long charge time when the pulse is terminated, a Schmitt trigger stage having a first and a second input, said first input being connected to the junction of the resistor and capacitor, a second stage having a reset input, an input connected to the output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and an output terminal connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state by the application of a pulse to the input terminal of a duration sufficient to discharge the capacitor to a voltage equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 12

A circuit as claimed in claim 8 in which the second stage is a gate operable to maintain the level of the voltage applied to the first input of the Schmitt trigger stage at a voltage below its second threshold level.

Claim 13

A circuit as claimed in claim 8 which includes a gate connected to the input terminal and having an output connected to junction of the resistor-capacitor and operable to extend the duration of an input pulse to ensure operation of the circuit.

Claim 14

A high speed priority circuit comprising at least one first input terminal to which a first pulse signal may be applied, at least one second terminal to which other pulse signals may be applied, and means for ensuring that said first input signal is given priority over the other input signals, said means including at least one high speed detection circuit connected to said first input terminal, said high speed detection circuit including a resistance-capacitance circuit connected to the first input terminal and arranged to have a short discharge time when said first pulse is terminated, a Schmitt trigger stage having a first and a second input and an output, said first input being connected to the resistance-capacitance circuit, a second stage having a reset input, an input connected to the output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and an output terminal connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state upon the application of a pulse to the first input terminal of a duration sufficient to discharge the capacitor of the resistance-capacitance circuit to a voltage equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 15

A high speed priority circuit comprising at least one first input terminal to which a first pulse signal may be applied, at least one second terminal to which other pulse signals may be applied, and means for ensuring that said first input signal is given priority over the other input signals, said means including at least one high speed detection circuit connected to said first input terminal, said high speed detection circuit including a resistance-capacitance circuit connected to the first input terminal and arranged to have a short discharge time when said first pulse is terminated, a Schmitt trigger stage having a first and a second input and an output, said first input being connected to the resistance-capacitance circuit, a second stage having a reset input, an input connected to the output of the Schmitt trigger stage and an output connected to said second input of the Schmitt trigger stage, and an output terminal connected to the output of the Schmitt trigger stage, the Schmitt trigger stage and the second stage forming a bistable loop which is set to one stable state upon the application of a pulse to the first input terminal of a duration sufficient to discharge the capacitor of the resistance-capacitance circuit to a voltage equal to a first threshold level of the Schmitt trigger stage, and is reset to the other stable state on the application of a pulse to the reset input of the second stage which allows the input of the Schmitt trigger stage to reach a second threshold level.

Claim 16

A circuit as claimed in claim 11 in which the second stage is a gate operable to maintain the input of the Schmitt trigger stage at a voltage below its second threshold level.

Claim 17

A circuit as claimed in claim 11 wherein said resistance-capacitance circuit includes a gate connected between said first input terminal and the junction of a serially connected resistor capacitor and being operable to extend the duration of an input pulse to ensure operation of the circuit.