High-speed/low-speed interface for data processing systems

Claim 2

In a data processing system having a first data-handling unit clocked by a low-speed clock and a second data-handling unit clocked by a high-speed clock, a single integrated circuit chip for transferring data in one direction either from said first unit to said second unit or from said second unit to said first unit, said integrated circuit chip comprising: A. a first portion fabricated to include low-speed circuitry to be clocked by a low-speed clock for processing data supplied thereto by a said first unit, said low-speed circuitry being connected to a first data input terminal, a first data output terminal and a low-speed clock input terminal; B. a second portion fabricated to include high-speed circuitry to be clocked by a high-speed clock for processing data supplied thereto by said second unit, said high-speed clock having a predetermined phase relationship to the low-speed clock and a pulse repetition frequency which is a whole number multiple of the pulse repetition frequency of the low-speed clock, said high speed circuitry being connected to a second data input terminal, a second data output terminal, and a high-speed clock input terminal; and C. a third portion fabricated to include interface circuitry for implementing the transfer of processed data in one direction from the low-speed circuitry to the high-speed circuitry or from the high-speed circuitry to the low-speed circuitry, said interface circuitry comprising: i. a first section including (a) first sampling means connected to receive processed data from one of either said high-speed circuitry said low-speed circuitry and connected to be clocked along with the circuitry from which it receives said processed data, said first sampling means serving to sample said processed data when it is clocked and (b) first storage means connected to said first sampling means for storing the sampled processed data, and having an output representative of the stored processed data; and ii. a second section including a. second sampling means connected to receive the output of the first storage means and connected to be clocked along with the other of said high-speed circuitry or said low-speed circuitry, the second sampling means serving to sample the first storage means output when said second sampling means is clocked and b. second storage means connected to said second sampling means for storing the sampled first storage means output, and having an output representative of the stored sampled output, said second storage means being further connected to deliver its output to said other circuitry.

Claim 3

A single integrated-circuit chip according to claim 1, wherein the major portion of the chip is fabricated to include said low-speed circuitry.

Claim 4

A single integrated-circuit chip as defined in claim 1 wherein all of said sampling means include MOS transistors, and all of said storage means are constituted by the inherent capacitance of the insulated gates of further MOS transistors.

Claim 5

A single integrated-circuit chip as defined in claim 1 further comprising logic functional elements each having an input and an output connected between at least one of said sampling means and its respective storage means, the input of each element being connected to the respective sampling means and said output being connected to the respective storage means, for logically processing said sampled processed data or said sampled output before it is stored.

Claim 6

A single integrated circuit chip as defined in claim 1 further comprising circuitry for implementing the transfer of processed data in the other direction comprising: i. a third section including a. third sampling means connected to receive processed data from the other of said high-speed circuitry of said low-speed circuitry and connected to be clocked along with the circuitry from which it receives processed data, said third sampling means serving to sample said processed data when it is clocked and b. third storage means connected to said third sampling means for storing the sampled processed data, and having an output representative of the stored processed data and ii. a fourth section including a. fourth sampling means connected to receive the output of the third storage means and connected to be clocked along with the one of said high-speed circuitry or said low-speed circuitry, the fourth sampling means serving to sample the third storage means output when said fourth sampling means is clocked and b. fourth storage means connected to said fourth sampling means, for storing the sampled third storage means output and having an output representative of the stored sample output, said fourth storage means being further connected to deliver its output to said one of said high-speed circuitry or said low-speed circuitry.

Claim 7

A single integrated circuit chip as defined in claim 5 in which said high-speed circuitry is to be clocked by a plurality of high-speed clocks and said low-speed circuitry is to be clocked by a plurality of low-speed clocks, said high-speed circuitry being connected to one high-speed clock input terminal for each high-speed clock by which it is to be clocked and said low-speed circuitry being connected to one low-speed clock input terminal for each low-speed clock by which it is to be clocked.

Claim 8

A single integrated circuit chip as defined in claim 6 in which the number of said high-speed clock input terminals is two and the number of low-speed clock input terminals is two.

Claim 9

A single integrated circuit chip as defined in claim 7 in which said first sampling means and said fourth sampling means are connected to be clocked by different clocks of the one of the high or low speed clocks and said second sampling means and said third sampling means are connected to be clocked by different clocks of the other of the high or low speed clocks.

Claim 10

A single integrated circuit chip as defined in claim 8 in which the low-speed clocks are to have the same pulse repetition frequency and differ by a predetermined phase relationship and said high-speed clocks are to have the same pulse repetition frequency and differ by a predetermined phase relationship, the frequency of said high-speed clocks being a whole-number multiple of the frequency of the low-speed clocks.

Claim 11

A single integrated-circuit chip as defined in claim 9 further including means for connecting together said clock input terminals supplying said first sampling means and said second sampling means and further including means for connecting together said clock input terminals supplying said third sampling means and said fourth sampling means to adapt the chip for use with multi-phase, single-speed circuitry.

Claim 12

Interface circuitry for implementing the transfer of data between high-speed circuitry and low-speed circuitry, the low-speed circuitry to be clocked by two low-speed clocks having the same pulse repetition frequency and differing by a predetermined phase factor, and the high-speed circuitry to be clocked by two high-speed clocks having the same pulse repetition frequency a whole-number multiple of the pulse repetition frequency of the low-speed clocks and differing by a predetermined phase factor, said interface circuitry comprising: A. a first section including i. first sampling means connected to receive data from said high-speed circuitry and connected to be clocked along with said high-speed circuitry, said first sampling means serving to sample said data when it is clocked and ii. first storage means connected to said first sampling means for storing the sampled data, and having an output representative of the stored data; and B. a second section including i. second sampling means connected to receive the output of the first storage means and connected to be clocked along with said low-speed circuitry, the second sampling means serving to sample the first storage means output when said second sampling means is clocked and ii. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said second storage means being further connected to deliver its output to said low-speed circuitry; and C. a third section including i. third sampling means connected to receive data from said low-speed circuitry and connected to be clocked along with said low-speed circuitry, said third sampling means serving to sample said data when said third sampling means is clocked and ii. third storage means connected to said third sampling means for storing the sampled data, and having an output representative of the stored sampled data D. a fourth section including i. fourth sampling means connected to receive the output of the third storage means and connected to be clocked along with said high-speed circuitry, the fourth sampling means serving to sample the third fourth storage means output when said fourth sampling means is clocked and ii. storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said fourth storage means being further connected to deliver its output to said high-speed circuitry.

Claim 13

Interface circuitry for implementing the transfer of data between high-speed circuitry and low-speed circuitry, the low-speed circuitry to be clocked by two low-speed clocks having the same pulse repetition frequency and differing by a predetermined phase factor, and the high-speed circuitry to be clocked by two high-speed clocks having the same pulse repetition frequency a whole-number multiple of the pulse repetition frequency of the low-speed clocks and differing by a predetermined phase factor, said interface circuitry comprising: A. a first section including i. first sampling means connected to receive data from said high-speed circuitry and connected to be clocked along with said high-speed circuitry, said first sampling means serving to sample said data when it is clocked and ii. first storage means connected to said first sampling means for storing the sampled data, and having an output representative of the stored data; and B. a second section including i. second sampling means connected to receive the output of the first storage means and connected to be clocked along with said low-speed circuitry, the second sampling means serving to sample the first storage means output when said second sampling means is clocked and ii. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said second storage means being further connected to deliver its output to said low-speed circuitry; and C. a third section including i. third sampling means connected to receive data from said low-speed circuitry and connected to be clocked along with said low-speed circuitry, said third sampling means serving to sample said data when said third sampling means is clocked and ii. third storage means connected to said third sampling means for storing the sampled data, and having an output representative of the stored sampled data D. a fourth section including i. fourth sampling means connected to receive the output of the third storage means and connected to be clocked along with said high-speed circuitry, the fourth sampling means serving to sample the third fourth storage means output when said fourth sampling means is clocked and ii. storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said fourth storage means being further connected to deliver its output to said high-speed circuitry.

Claim 14

Interface circuitry according to claim 11, wherein the interface circuitry is fabricated on a single integrated-circuit chip, the chip including a pair of high-speed input terminals for the high-speed clocks and a pair of low-speed input terminals for the low-speed clocks.

Claim 15

A single integrated-circuit chip according to claim 12, wherein the chip comprises a further portion fabricated to include high-speed circuitry to be clocked by the high-speed clock, and a further portion fabricated to include low-speed circuitry to be clocked by the low-speed clock.

Claim 16

A single integrated-circuit chip according to claim 13, wherein the major portion of the chip is fabricated to include said low-speed circuitry.

Claim 17

A single integrated-circuit chip as defined in claim 14, further comprising means for connecting together said clock input terminals supplying said first sampling means and said second sampling means, and further comprising means for connecting together said clock input terminals supplying said third sampling means and said fourth sampling means, to adapt the chip for use with multiphase single speed circuitry.

Claim 18

A single integrated-circuit chip as defined in claim 14 wherein all of said sampling means include MOS transistors, and all of said storage means are constituted by the inherent capacitance of the insulated gates of further MOS transistors.

Claim 19

A single integrated circuit chip as defined in claim 14 further comprising logic functional elements each having an input and an output connected between at least some of said sampling means and their respective storage means, with each input being connected to one of said sampling means and each output being connected to the respective storage means for logically processing said sampling data or said sampled output before it is stored.

Claim 20

In a data processing system having low-speed circuitry to be clocked by a low-speed clock and high-speed circuitry to be clocked by a high-speed clock having a predetermined phase relationship to the low-speed clock and a pulse repetition frequency which is a whole number multiple of the pulse repetition frequency of the low-speed clock, interface circuitry for implementing the transfer of data either from the low-speed circuitry to the high-speed circuitry or from the high-speed circuitry to the low-speed circuitry, said interface circuitry comprising: A. a first section including i. first sampling means connected to receive data from one of either said high-speed circuitry or said low-speed circuitry and connected to be clocked along with the circuitry from which it receives data, said first sampling means serving to sample said data when it is clocked and ii. first storage means connected to said first sampling means for storing the sampled data, and having an output representative of the stored data; and B. a second section including i. second sampling means connected to receive the output of the first storage means and connected to be clocked along with the other of said high-speed circuitry or said low-speed circuitry, the second sampling means serving to sample the said first storage means output when said second sampling means is clocked and (ii) second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sample output, said second storage means being further connected to deliver its output to said other circuitry.

Claim 21

In a data processing system having low-speed circuitry to be clocked by a low-speed clock and high-speed circuitry to be clocked by a high-speed clock having a predetermined phase relationship to the low-speed clock and a pulse repetition frequency which is a whole number multiple of the pulse repetition frequency of the low-speed clock, interface circuitry for implementing the transfer of data either from the low-speed circuitry to the high-speed circuitry or from the high-speed circuitry to the low-speed circuitry, said interface circuitry comprising: A. a first section including i. first sampling means connected to receive data from one of either said high-speed circuitry or said low-speed circuitry and connected to be clocked along with the circuitry from which it receives data, said first sampling means serving to sample said data when it is clocked and ii. first storage means connected to said first sampling means for storing the sampled data, and having an output representative of the stored data; and B. a second section including i. second sampling means connected to receive the output of the first storage means and connected to be clocked along with the other of said high-speed circuitry or said low-speed circuitry, the second sampling means serving to sample the said first storage means output when said second sampling means is clocked and (ii) second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sample output, said second storage means being further connected to deliver its output to said other circuitry.

Claim 22

In a data processing system having a first data-handling unit clocked by a low-speed clock and a second data-handling unit clocked by a high-speed clock, a single large-scale integrated circuit MOS chip for transferring data between said first unit and said second unit, said integrated circuit MOS chip comprising: A. a first portion fabricated to include low-speed circuitry for processing data supplied thereto by said first unit, said low-speed circuitry being connected to a first data input terminal, a first data output terminal and two low-speed clock input terminals, said low-speed circuitry to be clocked by a pair of low-speed clocks having the same pulse repetition frequency and differing by a predetermined phase relationship; B. a second portion fabricated to include high-speed circuitry for processing data supplied thereto by said second unit, said high-speed circuitry being connected to a second data input terminal, a second data output terminal and two high-speed clock input terminals, said high-speed circuitry to be clocked by a pair of high-speed clocks having the same pulse repetition frequency a whole-number multiple of the pulse repetition frequency of the low-speed clocks and differing by a predetermined phase relationship; and C. a third portion formed to include interface circuitry for implementing the transfer of processed data between the high-speed circuitry and the low-speed circuitry, said interface circuitry including: i. a first section including a. first sampling means connected to receive processed data from said high-speed circuitry and connected to be clocked along with said high-speed circuitry, said first sampling means serving to sample said processed data when it is clocked and b. first storage means connected to said first sampling means for storing the sampled processed data, and having an output representative of the stored processed data; and ii. a second section including a. second sampling means connected to receive the output of the first storage means and connected to be clocked along with said low-speed circuitry, the second sampling means serving to sample the first storage means output when said second sampling means is clocked and b. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said second storage means being further connected to deliver its output to said low-speed circuitry; and iii. a third section including a. third sampling means connected to receive processed data from said low-speed circuitry and connected to be clocked along with said low-speed circuitry, said third sampling means serving to sample the processed data when it is clocked and b. third storage means connected to said third sampling means for storing the sampled processed data, and having an output representative of the stored processed data; and iv. a fourth section including a. fourth sampling means connected to receive the output of the third storage means and connected to be clocked along with said high-speed circuitry, the fourth sampling means serving to sample the third storage means output when said second sampling means is clocked and b. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sample output, said fourth storage means being further connected to deliver its output to said high-speed circuitry.

Claim 23

In a data processing system having a first data-handling unit clocked by a low-speed clock and a second data-handling unit clocked by a high-speed clock, a single large-scale integrated circuit MOS chip for transferring data between said first unit and said second unit, said integrated circuit MOS chip comprising: A. a first portion fabricated to include low-speed circuitry for processing data supplied thereto by said first unit, said low-speed circuitry being connected to a first data input terminal, a first data output terminal and two low-speed clock input terminals, said low-speed circuitry to be clocked by a pair of low-speed clocks having the same pulse repetition frequency and differing by a predetermined phase relationship; B. a second portion fabricated to include high-speed circuitry for processing data supplied thereto by said second unit, said high-speed circuitry being connected to a second data input terminal, a second data output terminal and two high-speed clock input terminals, said high-speed circuitry to be clocked by a pair of high-speed clocks having the same pulse repetition frequency a whole-number multiple of the pulse repetition frequency of the low-speed clocks and differing by a predetermined phase relationship; and C. a third portion formed to include interface circuitry for implementing the transfer of processed data between the high-speed circuitry and the low-speed circuitry, said interface circuitry including: i. a first section including a. first sampling means connected to receive processed data from said high-speed circuitry and connected to be clocked along with said high-speed circuitry, said first sampling means serving to sample said processed data when it is clocked and b. first storage means connected to said first sampling means for storing the sampled processed data, and having an output representative of the stored processed data; and ii. a second section including a. second sampling means connected to receive the output of the first storage means and connected to be clocked along with said low-speed circuitry, the second sampling means serving to sample the first storage means output when said second sampling means is clocked and b. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sampled output, said second storage means being further connected to deliver its output to said low-speed circuitry; and iii. a third section including a. third sampling means connected to receive processed data from said low-speed circuitry and connected to be clocked along with said low-speed circuitry, said third sampling means serving to sample the processed data when it is clocked and b. third storage means connected to said third sampling means for storing the sampled processed data, and having an output representative of the stored processed data; and iv. a fourth section including a. fourth sampling means connected to receive the output of the third storage means and connected to be clocked along with said high-speed circuitry, the fourth sampling means serving to sample the third storage means output when said second sampling means is clocked and b. second storage means connected to said second sampling means for storing the sampled output, and having an output representative of the stored sample output, said fourth storage means being further connected to deliver its output to said high-speed circuitry.