US3696338A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data terminal-computer serial interface system having automatic baud rate switching
Assignee: Tektronix Inc
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Filing: 1970-08-20
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Granted: 1972-10-03
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Expires: 1990-08-20
Abstract
Abstract Interface circuits for transmitting digital information serially from a computer data terminal through a transmit data line to a computer and also in the reverse direction through a receive data line from the computer to the data terminal provide automatic electronic switching responsive to transmission of information through the transmit data line for disconnecting the pulse output of a high frequency clock from a single interface clock line, and at the same time connecting a lower frequency clock to this clock line. The clocks control transmit and receive registers in the interface to produce one rate of data transmission when no data is being transmitted in the direction from the data terminal to the computer and a lower rate of data transmission when data is being transmitted in such direction. A terminal busy inhibit signal from the data terminal may also be employed to prevent transmission of clock pulses by the clock line when the data terminal is not ready to receive data.
Inventors
- 👤 Richard B Preiss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
346 words
In an interface system for transmission of data in both directions between a computer data terminal and a computer, in which said system includes: data terminal interface means and computer interface means having data circuit means for concurrently transmitting serial data in both said directions between said interfaces and also transmitting clock pulses between said interfaces; data receiving means for said computer in said computer interface means and data transmitting means in said data terminal interface means for transmitting digital data from said data terminal in serial form to said data receiving means through said data circuit means under control of said clock pulses; data receiving means for said data terminal in said data terminal interface means and data transmitting means in said computer interface means for transmitting digital data from said computer in serial form to said data receiving means in said data terminal interface means through said data circuit means under control of said clock pulses; the improvement which comprises: clock circuit means for producing clock pulses at a first frequency corresponding to a digital data baud rate compatible with the rate at which the input circuits of said computer can accept digital data from said data terminal and for also producing clock pulses at a higher frequency than said first frequency and compatible with a digital data baud rate at which said computer can transmit digital data and said data terminal can accept digital data from said computer; and means responsive to the transmission of digital data through said data circuit means from said data terminal interface to said computer interface for causing said clock circuit means to supply clock pulses at said first frequency to both said interfaces during time periods in which digital data is being transmitted through said data circuit means from said data terminal interface to said computer interface and causing said clock circuit means to supply clock pulses at said higher frequency to said computer interface durIng time periods when data is not transmitted through said data circuit means from said data terminal interface to said computer interface.
Claim 2
Dependent Claim
346 words
In an interface system for transmission of data in both directions between a computer data terminal and a computer, in which said system includes: data terminal interface means and computer interface means having data circuit means for concurrently transmitting serial data in both said directions between said interfaces and also transmitting clock pulses between said interfaces; data receiving means for said computer in said computer interface means and data transmitting means in said data terminal interface means for transmitting digital data from said data terminal in serial form to said data receiving means through said data circuit means under control of said clock pulses; data receiving means for said data terminal in said data terminal interface means and data transmitting means in said computer interface means for transmitting digital data from said computer in serial form to said data receiving means in said data terminal interface means through said data circuit means under control of said clock pulses; the improvement which comprises: clock circuit means for producing clock pulses at a first frequency corresponding to a digital data baud rate compatible with the rate at which the input circuits of said computer can accept digital data from said data terminal and for also producing clock pulses at a higher frequency than said first frequency and compatible with a digital data baud rate at which said computer can transmit digital data and said data terminal can accept digital data from said computer; and means responsive to the transmission of digital data through said data circuit means from said data terminal interface to said computer interface for causing said clock circuit means to supply clock pulses at said first frequency to both said interfaces during time periods in which digital data is being transmitted through said data circuit means from said data terminal interface to said computer interface and causing said clock circuit means to supply clock pulses at said higher frequency to said computer interface durIng time periods when data is not transmitted through said data circuit means from said data terminal interface to said computer interface.
Claim 3
Dependent Claim
44 words
The system of claim 1 in which: said data receiving means in said computer interface means includes a data register for converting serial data to parallel data for use by said computer and said data register is connected for actuation by said clock pulses.
Claim 4
Dependent Claim
53 words
The system of claim 1 which also includes: another clock circuit means for producing clock pulses at a frequency at least closely approximating said first frequency; and said data receiving means in said computer interface is connected to said other clock circuit means for actuation by clock pulses from said other clock means.
Claim 5
Dependent Claim
241 words
The system in accordance with claim 1 in which: said data transmitting means in said data terminal interface means is a data register for converting data words of parallel data from said data terminal to serial data and delivering bits of said serial data in sequence to said circuit means; said electronic switching means includes switching circuit means normally causing said clock circuit means to supply pulses at said higher frequency; and includes transmitted data sensing means connected to said data circuit means for sensing each bit of data delivered through said circuit means from said data terminal interface to said computer interface and sending a switching signal to said switching circuit means for causing said clock circuit means to supply pulses at said first frequency beginning at the time a first bit of data in a sequence of said bits is delivered through said data circuit means from said data terminal interface to said computer interface; said transmitted data sensing means including time delay means for continuing said switching signal for a time beginning when the last bit of said sequence has been delivered through said data circuit means from said data terminal interface to said computer interface and extending for a period at least as great as the time required to transmit a serial data word through said data circuit means from said data terminal interface to said computer interface under control of said pulses at said first frequency.
Claim 6
Dependent Claim
60 words
The system in accordance with claim 4 in which: said transmitted data sensing means is a retriggerable monostable multivibrator triggered by each of said bits of data in said sequence and having a time out period after being triggered by one of said bits of data at least as great as said time required to transmit said serial data word.
Claim 7
Dependent Claim
50 words
The system of claim 1 in which: said electronic switching means includes means for receiving a terminal busy inhibit signal from said data terminal for preventing the delivery of clock pulses to said circuit means when said data terminal is busy and not ready to receive data from said computer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-03 | 1976-04-03 | 1976-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-03 | 1980-04-03 | 1980-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-03 | 1984-04-03 | 1984-10-03 | $7700.00 | Window Closed / Lapsed |