Device isolation in integrated circuits

Claim 1

A method of isolating circuit devices in a semiconductor body having first and second substantially parallel major planar surfaces and having at least two contiguous layers of distinct and different conductivity type the major portion of whose boundary lies substantially parallel to said planar surfaces, which comprises adherently forming on said first planar surface of said semiconductor body a thin film of polish-resistant material, etching grooves penetrating substantially normal to said first planar surface through said film and to a depth exceeding the depth of said boundary but short of said second planar surface of said semiconductor body, to define portions of said body encompassed by said grooves and in which circuit devices are to be fabricated, thermally growing an oxide isolation layer on exposed surfaces of said grooves, of insufficient thickness to fill said grooves, depositing polycrystalline film material on said oxide isolation layer in said grooves in sufficient quantity to fill the remainder of the grooves and overlie said thin film of polish-resistant material, polishing away the polycrystalline material in excess of that required to fill said grooves until said thin film is encountered to retard further removal and to prevent damage to said first planar surface of said semiconductor body, and fabricating circuit devices in said body adjacent said first planar surface thereof while leaving the portion of said body unpenetrated by said grooves intact to constitute a rigid support for said devices and to provide junction isolation between said two contiguous layers, with lateral isolation between devices within body portions encompassed by said grooves provided by said oxide isolation layer.

Claim 2

A method of isolating circuit devices in a semiconductor body having first and second substantially parallel major planar surfaces and having at least two contiguous layers of distinct and different conductivity type the major portion of whose boundary lies substantially parallel to said planar surfaces, which comprises adherently forming on said first planar surface of said semiconductor body a thin film of polish-resistant material, etching grooves penetrating substantially normal to said first planar surface through said film and to a depth exceeding the depth of said boundary but short of said second planar surface of said semiconductor body, to define portions of said body encompassed by said grooves and in which circuit devices are to be fabricated, thermally growing an oxide isolation layer on exposed surfaces of said grooves, of insufficient thickness to fill said grooves, depositing polycrystalline film material on said oxide isolation layer in said grooves in sufficient quantity to fill the remainder of the grooves and overlie said thin film of polish-resistant material, polishing away the polycrystalline material in excess of that required to fill said grooves until said thin film is encountered to retard further removal and to prevent damage to said first planar surface of said semiconductor body, and fabricating circuit devices in said body adjacent said first planar surface thereof while leaving the portion of said body unpenetrated by said grooves intact to constitute a rigid support for said devices and to provide junction isolation between said two contiguous layers, with lateral isolation between devices within body portions encompassed by said grooves provided by said oxide isolation layer.

Claim 9

A method of isolating circuit devices in a semiconductor body, comprising forming first and second contiguous layers of different conductivity type with a P-N junction therebetween in said body, providing an adherent layer of polish-resistant material on a planar surface of said body, etching grooves through said polish-resistant layer and partly penetrating said body to a depth exceeding the depth of said P-N junction, forming a dielectric isolation layer on the exposed surfaces of said grooves, overfilling the remainder of the grooves with adherent, high temperature-resistant material, polishing away the fill material in excess of that required to fill the grooves, said polish-resistant layer acting as a polishing stop to prevent damage to the underlying planar surface of the body portions between said grooves, said dielectric layer-coated grooves providing dielectric isolation and said P-N junction permitting junction isolation of circuit devices to be fabricated in said body portions between said grooves.

Claim 10

A method of isolating circuit devices in a semiconductor body, comprising forming first and second contiguous layers of different conductivity type with a P-N junction therebetween in said body, providing an adherent layer of polish-resistant material on a planar surface of said body, etching grooves through said polish-resistant layer and partly penetrating said body to a depth exceeding the depth of said P-N junction, forming a dielectric isolation layer on the exposed surfaces of said grooves, overfilling the remainder of the grooves with adherent, high temperature-resistant material, polishing away the fill material in excess of that required to fill the grooves, said polish-resistant layer acting as a polishing stop to prevent damage to the underlying planar surface of the body portions between said grooves, said dielectric layer-coated grooves providing dielectric isolation and said P-N junction permitting junction isolation of circuit devices to be fabricated in said body portions between said grooves.