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US3972033A
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Parity check system in a semiconductor memory
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-12-23
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Granted: 1976-07-27
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Expires: 1994-12-23
Abstract
Abstract A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two "bytes", of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Since an error cause affecting the control or the addressing circuits mounted on a card does not affect the recording and the addressing circuits of the second card, the recording or addressing of the information bits on one card will differ from the recording and addressing of the related check bit on the other card. Both bytes may be written or read out separately; and the writing or the reading-out signals of the information bits are independent from the writing or reading-out signal of the related check bits for both cards.
Inventors
- 👤 Ezio Cislaghi
- 👤 Claudio Gentili
- 👤 Ermanno Maccario
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:40
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1016; G06F11/1032
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A semiconductor memory for recording a plurality of memory words, each word comprising a plurality of information bits subdivided into a number of partial words, at least one chick bit assigned to each partial word, comprising: a plurality of integrated memory units, means for recording each partial word and the check bit assigned to said partial word respectively, on separate ones of said integrated memory units, and recording control means, including a plurality of control circuit means, for controlling the recording of the check bit assigned to each partial word independently of the recording of the information bits of said partial word.
Claim 2
Dependent Claim
102 words
A semiconductor memory for recording a plurality of memory words, each word comprising a plurality of information bits subdivided into a number of partial words, at least one chick bit assigned to each partial word, comprising: a plurality of integrated memory units, means for recording each partial word and the check bit assigned to said partial word respectively, on separate ones of said integrated memory units, and recording control means, including a plurality of control circuit means, for controlling the recording of the check bit assigned to each partial word independently of the recording of the information bits of said partial word.
Claim 3
Dependent Claim
124 words
The apparatus of claim 1 wherein said partial words of each memory word comprise first and second half-words, said memory comprising a plurality of submodules each including a pair of printed circuit cards, each of said cards carrying a number of said integrated memory units and of said control circuit means, the control circuit means on one card of each of said submodules being connected to record first half-words and check bits of the corresponding second half-words respectively, on the integrated memory units of said one card, the control circuit means on the other card of each of said submodules being connected to record second half-words and check bits of the corresponding first half-words respectively, on the integrated memory units of said other card.
Claim 4
Dependent Claim
48 words
The apparatus of claim 2 wherein said recording control means further include means for connecting said control circuit means to record the information bits of half-words addressed to integrated memory units on a card independently of check bits addressed to other integrated memory units on the same card.
Claim 5
Dependent Claim
61 words
A semiconductor memory, comprising:a plurality of circuit sections; means for recording different portions of an information word on different circuit sections; and means for recording a check bit for each of said different portions of said information word on a one of said circuit sections other than the circuit section upon which the corresponding portion of said information word is recorded.
Claim 6
Dependent Claim
61 words
A semiconductor memory, comprising:a plurality of circuit sections; means for recording different portions of an information word on different circuit sections; and means for recording a check bit for each of said different portions of said information word on a one of said circuit sections other than the circuit section upon which the corresponding portion of said information word is recorded.
Claim 7
Dependent Claim
26 words
A semiconductor memory, as recited in claim 4, wherein said different portions of an information word are half-words and said circuit sections are printed circuit cards.
Claim 8
Dependent Claim
185 words
A semiconductor memory for recording a plurality of memory words and related check bits, each word comprising a plurality of information bits subdivided into a number of partial words, at least one check bit assigned to each partial word, comprising: a first plurality of integrated memory units connected to receive a first partial word of each of said words, a second plurality of integrated memory units connected to receive a second partial word of each of said words, a third plurality of integrated memory units connected to receive the check bit assigned to a partial word, other than said first one, of each of said words, a fourth plurality of integrated memory units connected to receive the check bit assigned to a partial word, other than said second one, of each of said words, first control circuit means connected to apply a plurality of timed signals to said first and third plurality of memory units to control recording therein, and second control circuit means connected to apply a plurality of timed signals to said second and fourth plurality of memory units to control recording therein.
Claim 9
Dependent Claim
185 words
A semiconductor memory for recording a plurality of memory words and related check bits, each word comprising a plurality of information bits subdivided into a number of partial words, at least one check bit assigned to each partial word, comprising: a first plurality of integrated memory units connected to receive a first partial word of each of said words, a second plurality of integrated memory units connected to receive a second partial word of each of said words, a third plurality of integrated memory units connected to receive the check bit assigned to a partial word, other than said first one, of each of said words, a fourth plurality of integrated memory units connected to receive the check bit assigned to a partial word, other than said second one, of each of said words, first control circuit means connected to apply a plurality of timed signals to said first and third plurality of memory units to control recording therein, and second control circuit means connected to apply a plurality of timed signals to said second and fourth plurality of memory units to control recording therein.
Claim 10
Dependent Claim
66 words
A semiconductor memory as recited in claim 6 and further comprising a plurality of memory submodules each including first and second printed circuit cards, said first cards having mounted thereon said first and third pluralities of integrated memory units and said first control circuit means, said second cards having mounted thereon said second and fourth pluralities of integrated memory units and said second control circuit means.
References Cited (Backward Citations)
US3761898A
Cited
US3858187A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |