Patent US3971992A successfully refreshed from Google Patents.
US3971992A
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Apparatus for presetting receivers of the synthesizing type
Assignee: TRIO ELECTRONICS Inc
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Filing: 1974-09-17
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Granted: 1976-07-27
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Expires: 1994-09-17
Abstract
Abstract In a method of presetting a receiver of the synthesizing type wherein the ratio of frequency division of a frequency divider in a phase locked loop is set in accordance with the content of an up-down counter, a search signal and a write signal are generated for sweeping the up-down counter, the contents of the up-down counter are sequentially written in a memory device each time an intermediate frequency output is obtained, and the up-down counter is preset in accordance with a data read out of the memory device thereby enabling the receiver to receive the signal from a desired broadcasting station.
Inventors
- 👤 Noboru Saikaishi
- 👤 Tsuneo Yamada
- 👤 Tetsuo Takahashi
- 👤 Yukio Numata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:34
CPC Classifications
H; H03; H03J; H03J7/00; H03J7/18; H03J7/20; H03J7/28; H03J7/285; H03J5/00; H03J5/02; H03J5/0245; H03J5/0272; H03J5/0281
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
164 words
Apparatus for presetting a receiver comprising a memory device, and up-down counter constructed to send out control signals at the counts thereof corresponding to the opposite ends of a frequency band to which said receiver can respond and to exchange data with said memory, an address shift register for designating an address in said memory device, means for generating a search signal and a write signal, a flip-flop circuit conditioned by said search and write signals to be set and reset by said control signals when said search and write signals are supplied to said flip-flop circuit, and a gate circuit responsive to said flip-flop circuit and to detecting an intermediate frequency output for sending a write enabling signal to said memory device for storing the content of said up-down counter in said memory device and for sending a shift signal to said address shift register each time said intermediate frequency output is obtained between the set and reset states of said flip-flop circuit.
Claim 2
Dependent Claim
164 words
Apparatus for presetting a receiver comprising a memory device, and up-down counter constructed to send out control signals at the counts thereof corresponding to the opposite ends of a frequency band to which said receiver can respond and to exchange data with said memory, an address shift register for designating an address in said memory device, means for generating a search signal and a write signal, a flip-flop circuit conditioned by said search and write signals to be set and reset by said control signals when said search and write signals are supplied to said flip-flop circuit, and a gate circuit responsive to said flip-flop circuit and to detecting an intermediate frequency output for sending a write enabling signal to said memory device for storing the content of said up-down counter in said memory device and for sending a shift signal to said address shift register each time said intermediate frequency output is obtained between the set and reset states of said flip-flop circuit.
Claim 3
Dependent Claim
98 words
The apparatus according to claim 1 wherein said gate circuit G 0 comprises a NAND gate circuit (G 1 ), means to apply an intermediate frequency signal to one input of said NAND gate circuit (G 1 ), means to apply the output of said flip-flop circuit (FF 1 ) to the other input of said NAND gate circuit (G 1 ), means for applying the output of said NAND gate circuit to said address shift register (SR), and an inverter (G 2 ) connected between the output of said NAND gate circuit and said memory device (m).
Claim 4
Dependent Claim
238 words
The apparatus according to claim 1 which further comprises a search preset control circuit (SC) including a first AND gate circuit (G 3 ) connected to receive said search and write signals, a differentiating circuit (C 1 , R 2 ) for differentiating the output of said first AND gate circuit (G 3 ) to produce a pulse of a definite width, a second flip-flop circuit (FF 2 ) connected to be set by said pulse, a NOR gate circuit (G 4 ) for producing a start signal in response to the output of said second flip-flop circuit (FF 2 ) and one control signal (MIN) generated by said up-down counter (CNT uD ) at a minimum frequency to which the receiver can respond, a third flip-flop circuit (FF 3 ) connected to be set by said start signal, a second AND gate circuit (G 5 ) for generating an end signal in response to the output of said third flip-flop circuit (FF 3 ) and the other control signal (MAX) generated by said up-down counter at a maximum frequency to which the receiver can respond, means for applying said start signal and said end signal to said first mentioned flip-flop circuit (FF 1 ), and a delay circuit (R 3 , C 2 ) for delaying said end signal and for applying the delayed signal to the reset terminal of said third flip-flop circuit (FF 3 ).
Claim 5
Dependent Claim
14 words
The apparatus according to claim 3 wherein said delay circuit comprises an integrating circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-27 | 1980-01-26 | 1980-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-27 | 1984-01-26 | 1984-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-27 | 1988-01-26 | 1988-07-27 | $7700.00 | Window Closed / Lapsed |