Frequency regulation of voltage controlled oscillators using clock-driven digital counters

Claim 2

In an apparatus for regulating the output frequency of a voltage controlled oscillator wherein the apparatus includes an adjustable frequency divider comprising a first programmable digital counter disposed in the main regulating path of the oscillator and having N successively higher order cascaded stages each of which has an auxiliary S-bit parallel input responsive to digital command signals for individually adjusting the count of such stage, and wherein the output frequency of the oscillator is adjusted by an error signal derived from a compArison of the frequency at the first counter output and a reference frequency, an improved arrangement for adjusting the instantaneous count of the first counter, which comprises: a second digital counter independent of the main regulating path of the oscillator and having N successively higher order cascaded stages, each such stage including an auxiliary S-bit parallel output representative of the instantaneous count of such stage; a clock pulse generator; first means for coupling the output of the clock pulse generator to the count input of the lowest order stage of the second counter; N programmable storage means individually connectable to the N-stages of the first counter for programming the first counter with a count programmed in the storage means; second means for selectively coupling the auxiliary outputs of the stages of the second counter to the respective auxiliary inputs of the corresponding stages of the first counter; and third means for selectively coupling the auxiliary outputs of the stages of the second counter to the respective inputs of the N-storage means for writing prescribed counts of the second counter into the N-storage means.

Claim 3

Apparatus as defined in claim 1, further comprising N decoding means individually connectable to the auxiliary outputs of the stages of the second counter, and N means individually coupled to the outputs of the N decoding means for displaying a visual indication of the count of the associated second counter stage.

Claim 4

Apparatus as defined in claim 1, in which the clock pulse generator has separately energizable first and second outputs; each stage of the second counter has forward and reverse counting inputs; and the first coupling means connects the first output of the clock pulse generator to the forward counting input of the lowest stage of the second counter and further connects the second output of the clock pulse generator to the reverse counting input of the lowest stage of the second counter.

Claim 5

Apparatus as defined in claim 3, in which the clock pulse generator comprises, in combination, first and second gates each having first and second inputs, the output of the first gate constituting the first output of the clock pulse generator and the output of the second gate constituting the second output of the clock pulse generator; a third gate having first and second inputs; first and second flip-flop circuits; means for coupling one output of the first flip-flop circuit to the first input of the first gate; means for coupling the other output of the first flip-flop circuit to the first input of the third gate; means for coupling one output of the second flip-flop circuit to the first input of the second gate; means for coupling the other output of the second flip-flop circuit to the second input of the third gate; a fourth gate having first and second inputs; means including an R-C integrating path for feeding the output of the fourth gate back to the first input thereof; means for coupling the output of the third gate to the second input of the fourth gate; and means for coupling the output of the fourth gate in parallel to the second inputs of the first and second gates.

Claim 6

In an apparatus for regulating the output frequency of a voltage controlled oscillator which is disposed in the tuning stage of a signal-seeking communications receiver and which is adjustable to sweep a selected portion of the frequency band received by the receiver, the receiver having facilities for detecting within the swept band a signal whose amplitude exceeds a predetermined threshold, wherein the apparatus includes a first programmable digital counter having N successively higher order cascaded stages each of which has an auxiliary S-bit parallel input responsive to digital command signals for individually adjusting the count of such stage, the output frequency of the oscillator being divided by a factor proportional to the total count of the first counter; and wherein the output fRequency of the oscillator is adjusted by an error signal derived from a comparison of the divided frequency and a reference frequency, an improved arrangement for successively varying the instantaneous count of the first counter to sweep the frequency band and for terminating the sweep upon the detection of a signal having an amplitude above the threshold, which comprises: a second digital counter having N cascaded stages, each such stage including an auxiliary S-bit parallel output representative of the instantaneous count of such stage; a normally unoperated clock pulse generator; first means for coupling the output of the clock pulse generator to the counting input of the lowest order stage of the second counter; second means for individually coupling the auxiliary outputs of each stage of the second counter to the auxiliary inputs of the corresponding stages of the first counter to sweep a desired portion of the frequency band when the clock pulse generator is operated; normally deenergized switching means having a first input energizable to operate the clock pulse generated and to initiate the sweep of the frequency band and a second input energizable to disable the clock pulse generator to terminate the sweep; and means responsive to the reception of a signal having an amplitude above the threshhold for energizing the second input of the switching means.

Claim 7

In an apparatus for regulating the output frequency of a voltage controlled oscillator which is disposed in the tuning stage of a signal-seeking communications receiver and which is adjustable to sweep a selected portion of the frequency band received by the receiver, the receiver having facilities for detecting within the swept band a signal whose amplitude exceeds a predetermined threshold, wherein the apparatus includes a first programmable digital counter having N successively higher order cascaded stages each of which has an auxiliary S-bit parallel input responsive to digital command signals for individually adjusting the count of such stage, the output frequency of the oscillator being divided by a factor proportional to the total count of the first counter; and wherein the output fRequency of the oscillator is adjusted by an error signal derived from a comparison of the divided frequency and a reference frequency, an improved arrangement for successively varying the instantaneous count of the first counter to sweep the frequency band and for terminating the sweep upon the detection of a signal having an amplitude above the threshold, which comprises: a second digital counter having N cascaded stages, each such stage including an auxiliary S-bit parallel output representative of the instantaneous count of such stage; a normally unoperated clock pulse generator; first means for coupling the output of the clock pulse generator to the counting input of the lowest order stage of the second counter; second means for individually coupling the auxiliary outputs of each stage of the second counter to the auxiliary inputs of the corresponding stages of the first counter to sweep a desired portion of the frequency band when the clock pulse generator is operated; normally deenergized switching means having a first input energizable to operate the clock pulse generated and to initiate the sweep of the frequency band and a second input energizable to disable the clock pulse generator to terminate the sweep; and means responsive to the reception of a signal having an amplitude above the threshhold for energizing the second input of the switching means.

Claim 8

In an apparatus for regulating the output frequency of a voltage controlled oscillator wherein the apparatus includes a first programmable digital counter having N cascaded stages each of which has an auxiliary S-bit parallel input responsive to digital command signals for individually adjusting the count of such stage, the output frequency of the oscillator being divided by a factor proportional to the total count of the first counter; and wherein the output frequency of the oscillator is adjusted by an error signal derived from a comparison of the divided frequency and a reference frequency, an improved arrangement for adjusting the instantaneous count of the first counter, which comprises: a second digital counter having N successively higher order cascaded stages each such stage including an auxiliary S-bit parallel output representative of the instantaneous count of such stage; a clock pulse generator; first means for coupling the output of the clock pulse generator to the counting input of the lowest order stage of the second counter; N-storage means each having at least one externally adressable S-bit storage location; second means coupling the auxiliary output of each stage of the second counter to the associated one of the storage means for selectively writing the S-bit count of such stage into a then-addressed location of the associated storage means; N gating means individually connectable to the N-stages of the first and second counters and with the N-storage means, each gating means having an S-bit parallel output and first and second S-bit parallel inputs, each gating means being arranged to selectively interconnect said output with either the first or the second input thereof; third means for individually coupling to the first and second inputs of each of the N gating means the auxiliary outputs of the associated stages of the second counter and the S-bit contents of a then-addressed location of the associated storage means; and fourth means for individually coupling the outputs of the N gating means to the auxiliary inputs of the associated N-stages of the first counter.

Claim 9

In an apparatus for regulating the output frequency of a voltage controlled oscillator wherein the apparatus includes a first programmable digital counter having N cascaded stages each of which has an auxiliary S-bit parallel input responsive to digital command signals for individually adjusting the count of such stage, the output frequency of the oscillator being divided by a factor proportional to the total count of the first counter; and wherein the output frequency of the oscillator is adjusted by an error signal derived from a comparison of the divided frequency and a reference frequency, an improved arrangement for adjusting the instantaneous count of the first counter, which comprises: a second digital counter having N successively higher order cascaded stages each such stage including an auxiliary S-bit parallel output representative of the instantaneous count of such stage; a clock pulse generator; first means for coupling the output of the clock pulse generator to the counting input of the lowest order stage of the second counter; N-storage means each having at least one externally adressable S-bit storage location; second means coupling the auxiliary output of each stage of the second counter to the associated one of the storage means for selectively writing the S-bit count of such stage into a then-addressed location of the associated storage means; N gating means individually connectable to the N-stages of the first and second counters and with the N-storage means, each gating means having an S-bit parallel output and first and second S-bit parallel inputs, each gating means being arranged to selectively interconnect said output with either the first or the second input thereof; third means for individually coupling to the first and second inputs of each of the N gating means the auxiliary outputs of the associated stages of the second counter and the S-bit contents of a then-addressed location of the associated storage means; and fourth means for individually coupling the outputs of the N gating means to the auxiliary inputs of the associated N-stages of the first counter.

Claim 10

Apparatus as defined in claim 6, in which the apparatus further comprises means including a third digital counter for addressing each of the N-storage means.