US3970942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Anti-hunting system for valve operator circuit
Assignee: Sunoco Inc R&M
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Filing: 1975-01-02
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Granted: 1976-07-20
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Expires: 1995-01-02
Abstract
Abstract An anti-hunting system for use with a valve operator circuit which compares two trains of pulses to place a valve in the correct position. The anti-hunting system includes a J-K flip-flop circuit receiving a clock pulse train having an absolute time relationship with the input pulse trains. Also included in the valve operator circuit is a system having a shift register for controlling the energizing of the leads to a stepping motor controlling the valve position.
Inventors
- 👤 Robert Mayer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:50
CPC Classifications
B; B67; B67D; B67D7/00; B67D7/06; B67D7/74; B67D7/743; B67D7/744; G; G05; G05D; G05D11/00; G05D11/02; G05D11/13; G05D11/131; G05D11/132; G05B; G05B2219/00; G05B2219/30; G05B2219/36; G05B2219/36012; G05B2219/41; G05B2219/41122; G05B2219/41247; G05B2219/41326
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
315 words
A pulse rate comparison system for comparing two input pulse trains to control a stepping motor and having means for preventing hunting action, and comprising: a. a J-K flip-flop circuit, said J-K flip-flop comprising, i. a flip-flop circuit with a set terminal, a reset terminal and a clock terminal as input terminals and Q and Q output terminals, ii. a first AND gate having one input terminal designated as the J input terminal and a second input terminal connected to the Q output terminal, the output of said first AND gate being connected to the set input terminal of the flip-flop circuit, and iii. a second AND gate having one input terminal designated as the K input terminal and a second input terminal connected to the Q output terminal, the output of said second AND gate being connected to the reset input terminal of the flip-flop circuit; b. means for applying one of two input pulse trains to be compared to the J input terminal of the J-K flip-flop circuit; c. means for applying the remaining or second pulse train to the K input terminal of the J-K flip-flop circuit; d. means for combining the two input pulse trains to form a third pulse train having an absolute time relationship with the input pulse trains; e. means for applying the third pulse train to the clock pulse terminal of the J-K flip-flop circuit; and f. means, responsive to the state of the input and output terminals of the J-K flip-flop circuit, for controlling the energizing of the stepping motor so that the motor is moved into the correct position without hunting, whereby a control pulse for energizing the stepping motor is produced only when a pulse is received by either the J or K input terminals of the J-K flip-flop circuit which does not change the state of the output of the J-K flip-flop circuit.
Claim 2
Dependent Claim
315 words
A pulse rate comparison system for comparing two input pulse trains to control a stepping motor and having means for preventing hunting action, and comprising: a. a J-K flip-flop circuit, said J-K flip-flop comprising, i. a flip-flop circuit with a set terminal, a reset terminal and a clock terminal as input terminals and Q and Q output terminals, ii. a first AND gate having one input terminal designated as the J input terminal and a second input terminal connected to the Q output terminal, the output of said first AND gate being connected to the set input terminal of the flip-flop circuit, and iii. a second AND gate having one input terminal designated as the K input terminal and a second input terminal connected to the Q output terminal, the output of said second AND gate being connected to the reset input terminal of the flip-flop circuit; b. means for applying one of two input pulse trains to be compared to the J input terminal of the J-K flip-flop circuit; c. means for applying the remaining or second pulse train to the K input terminal of the J-K flip-flop circuit; d. means for combining the two input pulse trains to form a third pulse train having an absolute time relationship with the input pulse trains; e. means for applying the third pulse train to the clock pulse terminal of the J-K flip-flop circuit; and f. means, responsive to the state of the input and output terminals of the J-K flip-flop circuit, for controlling the energizing of the stepping motor so that the motor is moved into the correct position without hunting, whereby a control pulse for energizing the stepping motor is produced only when a pulse is received by either the J or K input terminals of the J-K flip-flop circuit which does not change the state of the output of the J-K flip-flop circuit.
Claim 3
Dependent Claim
23 words
The pulse rate comparison system recited in claim 1, wherein the means for combining the two input pulse trains includes a NAND gate.
Claim 4
Dependent Claim
125 words
The pulse rate comparison system recited in claim 1, wherein the means for controlling the energizing of the stepping motor comprises: a. means for summing the pulse trains from the J and K input terminals and Q and Q output terminals to produce a sum output pulse train having a pulse only when a pulse occurs on one of the input terminals of the J-K flip-flop circuit which does not change the state of the output of the J-K flip-flop circuit; and b. means, responsive to the sum output pulse train and the state of one of the output terminals of the J-K flip-flop circuit, for energizing the appropriate electrical leads of the stepping motor so that the motor is stepped into its correct position.
Claim 5
Dependent Claim
127 words
The pulse rate comparison system recited in claim 3, wherein the summing means comprises: a. a first NAND gate having one input terminal receiving the input pulse train applied to the J input terminal and a second input terminal receiving the pulse train experienced at the Q terminal of the J-K flip-flop circuit; b. a second NAND gate having one input terminal receiving the input pulse train applied to the K input terminal and a second input terminal receiving the pulse train experienced at the Q terminal of the J-K flip-flop circuit; and c. a third NAND gate having one input terminal receiving the output pulse train of the first NAND gate and a second input terminal receiving the output pulse train of the second NAND gate.
Claim 6
Dependent Claim
23 words
The pulse rate comparison system recited in claim 3, wherein the means for energizing the stepping motor electrical leads comprises a shift register.
Claim 7
Dependent Claim
97 words
The pulse rate comparison system recited in claim 5, wherein the shift register has a clock pulse terminal which receives the sum output pulse train and a parallel enable terminal connected to one of the J-K flip-flop circuit outputs, and means for interconnecting the stages of the shift register and the leads of the stepping motor so that upon receiving pulse trains with predetermined waveforms at the clock pulse terminal and the parallel enable terminal, the leads are energized in a predetermined manner, thereby causing the stepping motor to move a predetermined amount in a predetermined direction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-20 | 1980-01-19 | 1980-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-20 | 1984-01-19 | 1984-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-20 | 1988-01-19 | 1988-07-20 | $7700.00 | Window Closed / Lapsed |