LSI chip compensator for process parameter variations

Claim 2

Stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration with an FET active device and an FET load device; a compensating sense circuit integral with said substrate and comprising FET means, for detecting variations in the performance of said FET means resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; said FET means including a first FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET load device in said functional circuit, to said variations in process parameters; said FET means further including a second FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET active device in said functional circuit, to said variations in process parameters; an amplifier integral with said substrate and connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate correction voltage to the gate of the load device in each of said functional FET circuits to be regulated; whereby the load gate voltage for functional FET circuits is regulated so as to compensate for variations in the process parameters which obtain during the fabrication of the LSI chip.

Claim 3

Stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration; a compensating sense circuit integral with said substrate and comprising FET devices, for detecting variations in the performance of said devices resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; an amplifier integral with said substrate and connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate voltage to the gate of the load device in each of said functional FET circuits to be regulated; said compensating sense circuit further comprising: the first FET transistor having a minimum width, non-minimum length gate, with its drain connected to the drain potential, its source connected to the input of said amplifier and its gate connected to the load gate potential of the functional FET circuitries; a second FET transistor having a minimum length gate, with its drain connected to the source of said first transistor, its gate connected to said drain potential and its source connected through a diffused resistor, to ground potential; a third FET transistor having a larger than minimum width, larger than minimum length gate, with its source connected to the source of said second transistor, its gate connected to said load gate voltage and its drain connected to said drain potential; whereby a voltage signal is output on said output node which is the load gate voltage correction required to compensate for parametric variations detected.

Claim 4

Stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration; a compensating sense circuit integral with said substrate and comprising FET devices, for detecting variations in the performance of said devices resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; an amplifier integral with said substrate and connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate voltage to the gate of the load device in each of said functional FET circuits to be regulated; said compensating sense circuit further comprising: the first FET transistor having a minimum width, non-minimum length gate, with its drain connected to the drain potential, its source connected to the input of said amplifier and its gate connected to the load gate potential of the functional FET circuitries; a second FET transistor having a minimum length gate, with its drain connected to the source of said first transistor, its gate connected to said drain potential and its source connected through a diffused resistor, to ground potential; a third FET transistor having a larger than minimum width, larger than minimum length gate, with its source connected to the source of said second transistor, its gate connected to said load gate voltage and its drain connected to said drain potential; whereby a voltage signal is output on said output node which is the load gate voltage correction required to compensate for parametric variations detected.

Claim 5

The stabilization and control apparatus of claim 2, wherein said first, second, and third FET devices are of the enhancement mode type.

Claim 6

The stabilization and control circuit of claim 3, wherein said load device in said functional FET circuit is an FET of the enhancement type.

Claim 7

The stabilization and control apparatus of claim 2, wherein said first FET device is a depletion mode type, said second FET device is an enhancement mode type and said third FET device is an enhancement mode type.

Claim 8

The stabilization and control apparatus of claim 5, wherein said load device in said functional FET circuit is an FET device of the depletion type.

Claim 9

The stabilization and control apparatus of claim 2, wherein said amplifier further comprises: a differential amplifier having a fourth FET transistor with a gate connected to said output node of said compensating sense circuit and the source connected to the source of a fifth FET transistor having its gate connected to a reference potential; said fourth transistor having a drain connected through a resistor to a high potential source and forming a node at which said load gate voltage is produced.

Claim 10

A stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration with an FET active device and an FET load device; a compensating sense circuit integral with said substrate and comprising FET means, for detecting variations in the performance of said FET means resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; said FET means including a first FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET load device in said functional circuit to said variations in process parameters; said FET means further including a second FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET active device in said functional circuit to said variations in process parameters; an amplifier connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate correction voltage to the gate of the load device in each of said functional FET circuits to be regulated; whereby the load gate voltage for functional FET circuits is regulated so as to compensate for variations in the process parameters which obtained during the fabrication of the LSI chip.

Claim 11

A stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration with an FET active device and an FET load device; a compensating sense circuit integral with said substrate and comprising FET means, for detecting variations in the performance of said FET means resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; said FET means including a first FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET load device in said functional circuit to said variations in process parameters; said FET means further including a second FET means having a drain-to-source current whose response to said variations in process parameters is proportional to the response of the drain-to-source current in said FET active device in said functional circuit to said variations in process parameters; an amplifier connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate correction voltage to the gate of the load device in each of said functional FET circuits to be regulated; whereby the load gate voltage for functional FET circuits is regulated so as to compensate for variations in the process parameters which obtained during the fabrication of the LSI chip.

Claim 12

A stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration; a compensating sense circuit integral with said substrate and comprising FET devices, for detecting variations in the performance of said devices resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; an amplifier connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate voltage to the gate of the load device in each of said functional FET circuits to be regulated; said compensating sense circuit further comprising: the first FET transistor having a minimum width; non-minimum length gate, with its drain connected to the drain potential, its source connected to the input of said amplifier and its gate connected to the load gate potential of the functional FET circuitries; a second FET transistor having a minimum length gate, with its drain connected to the source of said first transistor, its gate connected to said drain potential and its source connected through a diffusion resistor, to ground potential; a third FET transistor having a larger than minimum width, larger than minimum length gate, with its source connected to the source of said second transistor, its gate connected to said load gate voltage and its drain connected to said drain potential; whereby a voltage signal is output on said output node which is the load gate voltage correction required to compensate for parametric variations detected.

Claim 13

A stabilization and control apparatus comprising: a semiconductor substrate containing a plurality of functional field effect transistor circuits in the linear load configuration; a compensating sense circuit integral with said substrate and comprising FET devices, for detecting variations in the performance of said devices resulting from variations in process parameters, and outputting a voltage with magnitude which varies in accordance with said variation in said process parameters; an amplifier connected to a reference potential, having an input connected to said output voltage from said compensating circuit, for outputting a load gate voltage to the gate of the load device in each of said functional FET circuits to be regulated; said compensating sense circuit further comprising: the first FET transistor having a minimum width; non-minimum length gate, with its drain connected to the drain potential, its source connected to the input of said amplifier and its gate connected to the load gate potential of the functional FET circuitries; a second FET transistor having a minimum length gate, with its drain connected to the source of said first transistor, its gate connected to said drain potential and its source connected through a diffusion resistor, to ground potential; a third FET transistor having a larger than minimum width, larger than minimum length gate, with its source connected to the source of said second transistor, its gate connected to said load gate voltage and its drain connected to said drain potential; whereby a voltage signal is output on said output node which is the load gate voltage correction required to compensate for parametric variations detected.

Claim 14

The stabilization and control apparatus of claim 9, wherein said first, second, and third FET devices are of the enhancement mode type.

Claim 15

The stabilization and control apparatus of claim 10, wherein said load device in said functional FET circuit is an FET of the enhancement type.

Claim 16

The stabilization and control apparatus of claim 9, wherein said first FET device is a depletion mode type, said second FET device is an enhancement mode type and said third FET device is an enhancement mode type.

Claim 17

The stabilization and control apparatus of claim 12, wherein said load device in said functional FET circuit is an FET device of the depletion type.

Claim 18

The stabilization and control apparatus of claim 9, wherein said amplifier constitutes circuit structure separate from said semiconductor substrate.