Integrated multiple transistors with different current gains

Claim 2

An integrated circuit comprising: a first multiple transistor and a second multiple transistor, which are formed in the same semiconductor body, each of which multiple transistors comprises: a vertical transistor having a collector region of a first conductivity type, a base region of a second conductivity type formed in said collector region, and an emitter region of the first conductivity type formed in said base region; and a lateral transistor having a base region of the second conductivity type, and an emitter region and a collector region of the first conductivity type laterally disposed in the surface of said base region, the base region of said lateral transistor being connected to the collector region of said lateral transistor and to the base region of said vertical transistor, the emitter region of said lateral transistor being connected to the emitter region of the vertical transistor; and wherein the lateral transistors of said first and second multiple transistors have respectively different current amplification factors.

Claim 3

A multiple transistor integrated circuit device including a semiconductor body and first and second multiple transistors formed in different portions of said body, each of said multiple transistors having a vertical and a lateral transistor portion and comprising: a first semiconductor layer, of a first conductivity type, as the collector region of said vertical transistor; a first semiconductor region of a second conductivity type, opposite said first conductivity type, disposed in a surface portion of said first semiconductor layer, as the common base region of said vertical transistor and said lateral transistor; and second and third semiconductor regions of said first conductivity type formed in spaced apart surface portions of said first semiconductor region, said second region being the emitter region of each of said vertical and lateral transistors and said third region being the collector region of said lateral transistor, and wherein said first and third regions are short circuited to each other; and wherein the lateral transistors in said first and second multiple transistors are different from one another with respect to at least one of the base width, which is the distance between said second and third regions, and the area and peripheral length of said third region.

Claim 4

A multiple transistor integrated circuit device including a semiconductor body and first and second multiple transistors formed in different portions of said body, each of said multiple transistors having a vertical and a lateral transistor portion and comprising: a first semiconductor layer, of a first conductivity type, as the collector region of said vertical transistor; a first semiconductor region of a second conductivity type, opposite said first conductivity type, disposed in a surface portion of said first semiconductor layer, as the common base region of said vertical transistor and said lateral transistor; and second and third semiconductor regions of said first conductivity type formed in spaced apart surface portions of said first semiconductor region, said second region being the emitter region of each of said vertical and lateral transistors and said third region being the collector region of said lateral transistor, and wherein said first and third regions are short circuited to each other; and wherein the lateral transistors in said first and second multiple transistors are different from one another with respect to at least one of the base width, which is the distance between said second and third regions, and the area and peripheral length of said third region.

Claim 5

A multiple transistor integrated circuit device according to claim 2, wherein each of said multiple transistors further includes a semiconductor substrate of said second conductivity type, upon which said first semiconductor layer is disposed, and a buried fourth semiconductor region of said first conductivity type overlapping the interface of said first semiconductor layer and said substrate beneath said first semiconductor region.

Claim 6

A multiple transistor integrated circuit device according to claim 2, wherein the distance between the second and third semiconductor regions of said first multiple transistor is greater than the distance between the second and third semiconductor regions of said second multiple transistor.

Claim 7

A multiple transistor integrated circuit device according to claim 4, wherein the surface area of the third semiconductor region of said first multiple transistor is different from the surface area of the third semiconductor region of said second multiple transistor.

Claim 8

A multiple transistor integrated circuit device according to claim 2, wherein the surface area of the third semiconductor region of said first multiple transistor is different from the surface area of the third semiconductor region of said second multiple transistor.