Electronic computer with independent functional networks for simultaneously carrying out different operations on the same data

Claim 2

An electronic computer for manipulating data comprising: a control unit; a working storage unit for storing information including data and program instructions; a first group of working registers; a second group of work registers; a logic-arithmetic unit comprising a plurality of different independent functional network units for performing different operations on said data, each having input and output terminals and each being coupled to said control unit; a first distributing channel circuit means for connecting said first group of work registers to the input terminals of each of said functional network units; a second distributing channel circuit means for connecting said second group of work registers to each of said functional network units; a collector channel circuit connecting the output terminals of each of said functional units to said first group of working registers; a plurality of decoding networks connected to the output terminals of at least a number of said functional units for signaling the results of certain ones of said different operations and a plurality of gate circuit means connecting said input terminals of each of said functional units to said first and second channel distribution circuit means, said gate circuit means being connected to be enabled selectively by said control unit for transferring simultaneously the same data from one of said working registers to at least a pair of said independent functional units conditioned by said control unit for performing different operations thereon during the processing of one of said program instructions, said pair including one of said number of units having its output terminals connected to a corresponding one of said decoding networks.

Claim 3

The computer of claim 1 wherein said plurality of functional independent units comprises an arithmetic network, a logic network and a shift network.

Claim 4

The computer of claim 2 wherein said plurality of independent functional units further comprises a comparison network.

Claim 5

A data processing system comprising: control means; working storage means for storing units of information representative of instructions and data for at least one program; logic and arithmetic means coupled to said control means and to said storage means, said logic and arithmetic means including a plurality of independent functionally different processing network means, each being individually coupled to said control means and having input and output terminals; distribution circuit means coupled to said working storage means for receiving said information; a plurality of gating means coupled to said distribution circuit means and each coupled to the input terminals of a different predetermined one of said processing network means; and, said control means being coupled to each of said gating means, said control means being operative to process one of said program instructions said control means in response to said one of said program instructions generating a series of subcommand signals for enabling at least a pair of said gating means to apply the same units of data simultaneously to corresponding ones of said processing network means and for causing each of said corresponding ones of said processing network means for performing different types of operations upon the same units of data.

Claim 6

A data processing system comprising: control means; working storage means for storing units of information representative of instructions and data for at least one program; logic and arithmetic means coupled to said control means and to said storage means, said logic and arithmetic means including a plurality of independent functionally different processing network means, each being individually coupled to said control means and having input and output terminals; distribution circuit means coupled to said working storage means for receiving said information; a plurality of gating means coupled to said distribution circuit means and each coupled to the input terminals of a different predetermined one of said processing network means; and, said control means being coupled to each of said gating means, said control means being operative to process one of said program instructions said control means in response to said one of said program instructions generating a series of subcommand signals for enabling at least a pair of said gating means to apply the same units of data simultaneously to corresponding ones of said processing network means and for causing each of said corresponding ones of said processing network means for performing different types of operations upon the same units of data.

Claim 7

The system according to claim 4 wherein said distribution circuit means includes first and second channel circuit means coupled to said plurality of gating means and wherein said system further includes; a first group of working register means for storing units of information read from said storage means corresponding to a first operand required for the execution of said one of said instruction, said first group of working register means being coupled to said first channel circuit means; a second group of working register means for storing units of information from said storage means corresponding to a second operand required for the execution of said one instruction, said second group of working register means being coupled to said second channel circuit means; and said control means being coupled to said first and second groups of working register means, said control means being operative to condition selectively said first and second group of working register means to apply one of said units of information representative of one of said operands to said pair of gating means enabling said different types of operations to be performed simultaneously on the same unit of information.

Claim 8

The system of claim 5 wherein said arithmetic-logic means further includes: a plurality of decoder means, each being coupled to the output terminals of a predetermined one of said processing network means, said control means being coupled to each of said decoder means and operative to enable one of said plurality of decoder means for receiving output signals from said predetermined one of said processing network means for receiving the results of one of said different operations performed upon said same unit of information.

Claim 9

The system of claim 6 further including: collector channel means coupled to said first group of working register means; and, a plurality of output gating means coupled to said collector channel means and to the output terminals of different ones of each of said processing network means, each of said output gating means being coupled to said control means and operative when enabled by said control means to apply signals present at said output terminals representative of the result of an operation performed by corresponding ones of said processing network means to said collector channel means for storage in selected ones of said first group of said working register means.

Claim 10

The system of claim 7 wherein said plurality of said processing network means includes: a shift network coupled to said control means and being enabled by said control means to shift by predetermined amounts said units of information; an arithmetic network coupled to said control means and being enabled by said control means to perform arithmetic operations upon said units; and, a logic network coupled to said control means and being enabled by said control means to perform logical operations upon said units.

Claim 11

The system of claim 7 wherein said arithmetic-logic means further includes: first gating means coupled said output terminals of said arithmetic network to a first one of said plurality of decoder means, said gating means being operatively coupled to said control means and when enabled by said control means to apply signals corresponding to the results of an operation performed upon said units to said first one of said decoder means for detecting predetermined bit patterns; and, second gating means coupling said output terminals of said logic network to a second one of said plurality of said decoder means, said gating means being operatively coupled to said control means and when enabled by said control means to apply signals corresponding to the results of an operation performed upon said unit to said second one of said decoder means for detecting said predetermined bit patterns.

Claim 12

The system of claim 8 wherein said plurality of said processing network means further includes a compare network operatively coupled to said control means for comparing said units of data with a predetermined value stored in one of said second group of working register means.

Claim 13

A data processing system comprising: storage means for storing information bytes representative of instructions and data pertinent to the execution of at least one program; an addressable microprogrammed control store including a plurality of microprograms each having a plurality of microinstructions for executing said instructions and control means for generating subcommand control signals in response to said microinstructions read out from said control store; processing means coupled to said storage means, said processing means including a plurality of independently operated functionally different network means, each having input and output terminals and being individually coupled to said control store for receiving said subcommand control signals; a first group of addressable working registers for storing information bytes received from said storage means and being coupled to said control store; a second group of addressable working registers for storing information bytes received from said storage means and being coupled to said control store; a first distributor channel means coupled to said first group of addressable working registers for receiving bytes read out from addressed ones of said first group of registers; a second distributor channel means coupled to said second group of addressable working registers for receiving bytes read out from addressed ones of said second group of registers; and, a plurality of gating means for selectively coupling said first and second distributor channel means to said inputs of said network means; said control means being responsive during the execution of one of said instructions to microinstructions read out from said control store to generate subcommand control signals for enabling at least a pair of said gating means to apply the same unit of information from one of said distributor channel means to the input terminals of corresponding ones of said network means and each of said corresponding ones of said network means being enabled by certain ones of said subcommand control signals to perform a different operation upon said same unit of information.

Claim 14

A data processing system comprising: storage means for storing information bytes representative of instructions and data pertinent to the execution of at least one program; an addressable microprogrammed control store including a plurality of microprograms each having a plurality of microinstructions for executing said instructions and control means for generating subcommand control signals in response to said microinstructions read out from said control store; processing means coupled to said storage means, said processing means including a plurality of independently operated functionally different network means, each having input and output terminals and being individually coupled to said control store for receiving said subcommand control signals; a first group of addressable working registers for storing information bytes received from said storage means and being coupled to said control store; a second group of addressable working registers for storing information bytes received from said storage means and being coupled to said control store; a first distributor channel means coupled to said first group of addressable working registers for receiving bytes read out from addressed ones of said first group of registers; a second distributor channel means coupled to said second group of addressable working registers for receiving bytes read out from addressed ones of said second group of registers; and, a plurality of gating means for selectively coupling said first and second distributor channel means to said inputs of said network means; said control means being responsive during the execution of one of said instructions to microinstructions read out from said control store to generate subcommand control signals for enabling at least a pair of said gating means to apply the same unit of information from one of said distributor channel means to the input terminals of corresponding ones of said network means and each of said corresponding ones of said network means being enabled by certain ones of said subcommand control signals to perform a different operation upon said same unit of information.

Claim 15

The system of claim 11 wherein said processing means further includes: a plurality of decoder means, each being coupled to the output terminals of a different predetermined one of said processing network means, said control means being coupled to each of said decoder means and operative to enable one of said plurality of decoder means for receiving output signals from said predetermined one of said network means for testing the results of one of said different operations performed upon said same unit of information.

Claim 16

The system of claim 12 further including: collector channel means coupled to said first group of working register means; and, a plurality of output gating means coupled to said collector channel means and to the output terminals of different ones of each of said network means, each of said output gating means being coupled to said control means and operative when enabled by said control signals to apply signals representative of the result of an operation performed by corresponding ones of said network means to said collector channel means for storage in selected ones of said first group of said working registers.

Claim 17

The system of claim 13 wherein said plurality of said network means includes: a shift network coupled to said control means, said shift network being operative in response to said subcommand control signals to shift by specified amounts said units of information; an arithmetic network coupled to said control means, said arithmetic network being operative in response to said subcommand control signals to perform specified operations upon said units; and, a logic network coupled to said control means, said logic network being operative in response to said subcommand control signals to perform specified logical operations upon said units.

Claim 18

The system of claim 13 wherein said arithmetic-logic means further includes: first gating means coupling said output terminals of said arithmetic network to a first one of said plurality of decoder means, said gating means being coupled to said control means and operative when enabled by said subcommand control signals to apply output signals to said first one of said decoder means for detecting predetermined bit patterns to test the result of an operation performed by said arithmetic network; and, second gating means coupling said output terminals of said logic network to a second one of said plurality of said decoder means, said gating means being coupled to said control means and operative when enabled by said subcommand control signals to apply output signals to said second one of said decoder means for detecting predetermined bit patterns to test the results of an operation performed by said logic network.

Claim 19

The system of claim 14 wherein said plurality of said network means further includes a compare network coupled to said control means, said compare network in response to said subcommand control signals being operative to compare said units of data with a value stored in one of said working registers.