Method of MOS transistor manufacture

Claim 1

A method of manufacturing a semiconductor structure having spaced diffused regions for source and drain elements and a gate region therebetween, said gate region including an overlying electrode insulatively spaced therefrom and ohmically connected to one of said diffused regions, comprising the steps of: a. forming an insulating layer over the surface of a semiconductor substrate including the area for said structure; b. defining and etching a first opening in said insulating layer thereby exposing a first area of the surface of said substrate for a first of said diffused regions; c. forming a layer of polycrystalline silicon over said insulating layer and within said first opening; d. defining and etching said polycrystalline silicon layer over said first area thereby exposing a portion of said first area such that a portion of said polycrystalline silicon layer remains in contact with the surface of said substrate and the remainder of said polycrystalline silicon layer extends from said first area over said insulating layer adjacent to said first area; e. defining and etching a second opening in said insulating layer adjacent to said polycrystalline silicon layer and spaced from said first area thereby exposing a second area of the surface of said substrate; f. diffusing an impurity into the structure thereby rendering said polycrystalline silicon layer conductive as a gate electrode, and thereby forming said first and second diffused regions in said substrate beneath said first and second areas of the surface of said substrate, wherein said gate electrode is formed in ohmic contact with said first region.

Claim 2

A method of manufacturing a semiconductor structure having spaced diffused regions for source and drain elements and a gate region therebetween, said gate region including an overlying electrode insulatively spaced therefrom and ohmically connected to one of said diffused regions, comprising the steps of: a. forming an insulating layer over the surface of a semiconductor substrate including the area for said structure; b. defining and etching a first opening in said insulating layer thereby exposing a first area of the surface of said substrate for a first of said diffused regions; c. forming a layer of polycrystalline silicon over said insulating layer and within said first opening; d. defining and etching said polycrystalline silicon layer over said first area thereby exposing a portion of said first area such that a portion of said polycrystalline silicon layer remains in contact with the surface of said substrate and the remainder of said polycrystalline silicon layer extends from said first area over said insulating layer adjacent to said first area; e. defining and etching a second opening in said insulating layer adjacent to said polycrystalline silicon layer and spaced from said first area thereby exposing a second area of the surface of said substrate; f. diffusing an impurity into the structure thereby rendering said polycrystalline silicon layer conductive as a gate electrode, and thereby forming said first and second diffused regions in said substrate beneath said first and second areas of the surface of said substrate, wherein said gate electrode is formed in ohmic contact with said first region.